Backdoor attack, where an adversary poisons the model by misclassifying inputs into an attacker-defined label, shows its uprising threats on deep learning models. Detecting and pruning backdoor neurons has emerged as an effective defense, however, precise mitigation of backdoor neurons from benign ones remains a challenge. Most existing works focus on exploiting empirical characteristics of backdoor neurons, such as their sensitivity to adversarial perturbations or asymmetric learning behavior, while overlooking their theoretical definition. In this paper, we propose a novel backdoor neuron ranking and pruning framework named DeepCurer , where we quantify each neuron’s impact on both clean and backdoor tasks and rank-and-prune them based on the inherent definition of backdoor neurons. To enable effective use of our method in the absence of poisoned samples, we demonstrate that targeted adversarial examples can serve as proxies. We also introduce a lightweight technique to detect target labels using adversarial proxies. A progressive neuron rank-and-prune algorithm is further developed to systematically remove backdoor neurons and sanitize underlying deep learning models. Experimental results show our proposed method can effectively mitigate backdoor neurons against ten state-of-the-art backdoor attacks at ultra-low poisoning ratios ( < =1%) while preserving the model’s clean performance. DeepCurer also upholds its superior performance by comparing against other state-of-the-art backdoor defense methods. The code is publicly available at GitHub repository .

Emerging in recent years, open edge computing platforms (OECPs) claim large-scale edge nodes, the extensive usage and adoption, as well as the openness to any third parties to join as edge nodes. For instance, OneThingCloud, a major OECP operated in China, advertises 5 million edge nodes, 70TB bandwidth, and 1,500PB storage. However, little information is publicly available for such OECPs with regards to their technical mechanisms and involvement in edge computing activities. Furthermore, different from known edge computing paradigms, OECPs feature an open ecosystem wherein any third party can participate as edge nodes and earn revenue for the contribution of computing and bandwidth resources, which, however, can introduce byzantine or even malicious edge nodes and thus break the traditional threat model for edge computing. In this study, we conduct the first empirical study on two representative OECPs, which is made possible through the deployment of edge nodes across locations, the efficient and semi-automatic analysis of edge traffic as well as the carefully designed security experiments. As the results, a set of novel findings and insights have been distilled with regards to their technical mechanisms, the landscape of edge nodes, the usage and adoption, and the practical security/privacy risks. Particularly, millions of daily active edge nodes have been observed, which feature a wide distribution in the network space and the extensive adoption in content delivery towards end users of 16 popular Internet services. Also, multiple practical and concerning security risks have been identified along with acknowledgements received from relevant parties, e.g., the exposure of long-term and crossedge-node credentials, the co-location with malicious activities of diverse categories, the failures of TLS certificate verification, the extensive information leakage against end users, etc.

OBJECTIVE: This study aims to explore the impact of different ROI delineation strategies on the axillary lymph nodes metastasis (ALNM) prediction model by analyzing two-dimensional ultrasound images of lymph nodes. In addition, we integrated clinical and pathological information to construct a comprehensive model, and based on this model, developed a nomogram for individualized assessment of the probability of ALNM. METHODS: A total of 146 axillary lymph nodes were randomly divided into a training set and a testing set at a ratio of 8:2. Clinical and pathological features were selected using univariate and multivariate logistic regression analyses, followed by the construction of a clinical prediction model. Radiomic features were extracted from both the internal and surrounding regions of the two-dimensional ultrasound images of the axillary lymph nodes. The least absolute shrinkage and selection operator (LASSO) algorithm was then used to select and retain the optimal features, followed by the construction of a radiomic prediction model. A combined prediction model was developed by integrating the clinical and radiomic models, and a nomogram was created for the combined prediction model. RESULTS: The clinical status of axillary lymph nodes was an independent predictor for metastasis. The clinical prediction model based on the status of axillary lymph nodes achieved an AUC of 0.728 in the testing set. The radiomic prediction model based on the LASSO logistic regression algorithm with a 1 mm extended region had the highest AUC of 0.856 in the testing set. The combined prediction model integrating the clinical and optimal radiomic models achieved an AUC of 0.841 in the testing set, with a sensitivity of 77.4% and an accuracy of 79.5%. This combined model outperformed the individual clinical and radiomic models and was more effective in predicting axillary lymph node metastasis. CONCLUSION: This study developed a predictive model for ALNM based on ultrasound images of ALNs and their peripheral extended regions. The results demonstrated that the combined model incorporating both the lymph node and a 1-mm peripheral extension yielded the best predictive performance. Furthermore, a comprehensive integrated model was established by incorporating clinical and pathological characteristics, which effectively enhanced the prediction of ALNM.

MOTIVATION: Primer design is a routine practice for modern molecular biology labs. Bioinformatics tools like primer3 and primer-blast have standardized the primer design for a specific region. However, large-scale primer design, especially for genome-wide screening, is still a labor-intensive job for most wet-lab researchers using these pipelines. RESULTS: Here, we present the primerdiffer pipeline, which can be used to batch design primers that differentiate haplotypes on a large scale with precise false priming checking. This command-line interface (CLI) pipeline includes greedy primer search, local and global in silico PCR-based false priming checking, and automated best primer selection. The local CLI application provides flexibility to design primers with the user's own genome sequences and specific parameters. Some species-specific primers designed to genotype the hybrid introgression strains from Caenorhabditis briggsae and Caenorhabditis nigoni have been validated using single-worm PCR. This pipeline provides the first CLI-based large-scale primer design tool to differentiate haplotypes in any targeted region. AVAILABILITY AND IMPLEMENTATION: The open-source python modules are available at github (https://github.com/runsheng/primerdiffer, https://github.com/runsheng/primervcf) and Python package index (https://pypi.org/project/primerdiffer/, https://pypi.org/project/primervcf/).

Over past years, the high demand to efficiently process deep learning (DL) models has driven the market of the chip design companies. However, the new Deep Chip architectures, a common term to refer to DL hardware accelerator, have slightly paid attention to the security requirements in quantized neural networks (QNNs), while the black/white -box adversarial attacks can jeopardize the integrity of the inference accelerator. Therefore in this paper, a comprehensive study of the resiliency of QNN topologies to black-box attacks is examined. Herein, different attack scenarios are performed on an FPGA-processor co-design, and the collected results are extensively analyzed to give an estimation of the impact's degree of different types of attacks on the QNN topology. To be specific, we evaluated the sensitivity of the QNN accelerator to a range number of bit-flip attacks (BFAs) that might occur in the operational lifetime of the device. The BFAs are injected at uniformly distributed times either across the entire QNN or per individual layer during the image classification. The acquired results are utilized to build the entropy-based model that can be leveraged to construct resilient QNN architectures to bit-flip attacks.

The study of Service Function Chains (SFCs) placement problem is crucial to support services flexibly and use resources efficiently. Solutions should satisfy various Quality of Service requirements, avoid edge resource congestion, and improve service acceptance ratio (SAR). This work presents a novel approach to address these challenges by solving amulti-objective SFCs placementproblem based on the Pointer Network in multi-layer edge and cloud networks. We design a Deep Reinforcement Learning algorithm, calledChebyshev-assisted Actor-Critic SFCs Placement Algorithm, to overcome the limitations of traditional heuristic and evolutionary algorithms. Then, we run this algorithm iteratively with a set of weights to obtain non-dominated fronts, which have much higher hypervolume values than those obtained from other state-of-the-art algorithms. Moreover, running our algorithm individually with selected weights from non-dominated fronts can avoid edge resource congestion and achieve 98% SARs of low-latency services during high-workload periods. Finally, based on both simulation and real testbed experimental results, it is validated that the proposed algorithm fits for pragmatic service deployment while achieving 100% of SARs in the use cases deployed on the testbed.

We propose SHIELDeNN, an end-to-end inference accelerator frame-work that synergizes the mitigation approach and computational resources to realize a low-overhead error-resilient Neural Network (NN) overlay. We develop a rigorous fault assessment paradigm to delineate a ground-truth fault-skeleton map for revealing the most vulnerable parameters in NN. The error-susceptible parameters and resource constraints are given to a function to find superior design. The error-resiliency magnitude offered by SHIELDeNN can be adjusted based on the given boundaries. SHIELDeNN methodology improves the error-resiliency magnitude of cnvW1A1 by 17.19% and 96.15% for 100 MBUs that target weight and activation layers, respectively.

In recent years, the big data booming has boosted the development of highly accurate prediction models driven from machine learning (ML) and deep learning (DL) algorithms. These models can be orchestrated on the customized hardware in the safety-critical missions to accelerate the inference process in ML/DL -powered IoT. However, the radiation-induced transient faults and black/white -box attacks can potentially impact the individual parameters in ML/DL models which may result in generating noisy data/labels or compromising the pre-trained model. In this paper, we propose Fiji-FIN1, a suitable framework for evaluating the resiliency of IoT devices during the ML/DL model execution with respect to the major security challenges such as bit perturbation attacks and soft errors. Fiji-FIN is capable of injecting both single bit/event flip/upset and multi-bit flip/upset faults on the architectural ML/DL accelerator embedded in ML/DL -powered IoT. Fiji-FIN is significantly more accurate compared to the existing software-level fault injections paradigms on ML/DL -driven IoT devices.

To meet the challenge of flexible and dynamic resource provisioning for massive and various network services, we investigate the network function virtualization-resource allocation problem in the 5G network. For the first time, this problem is modelled as the congestion game to capture the effects of resource congestion on packet processing latency, optical-to-electronic and electronic-to-optical conversion latency. All the network service requests received at the same time are players trying to minimise their own end-to-end latency and resource consumption cost. A distributed online algorithm is designed and simulation results show that it can achieve 100% service acceptance ratio while the baseline algorithm cannot. If lower weighted resource consumption cost is set for 1ms and 5ms services, more such services will be routed to edge nodes and network operators will earn more. An experiment for network services with different packet sizes is carried out, and results prove that the proposed algorithm converges to Nash Equilibrium in 40 seconds and the latency requirements are all satisfied if the packet size is small.

To support ultra-low latency 5G services flexibly and use limited resources in Multi-access Edge Computing (MEC) servers efficiently, the study of latency-aware optimal hierarchical resource allocation for Service Function Chains in 5G becomes essential. In this regard, we address this resource allocation problem, for the first time, by designing a Mixed Integer Linear Programming (MILP) model based on a hierarchical 5G network interconnecting multiple MEC nodes. The objective is to minimize the total latency from five sources: processing, queueing, transmission, propagation, and optical-electronic-optical conversion. Experimental results prove that ultra-low latency requirements can be guaranteed and maximum usage of MEC node resources can be obtained. Then, a data rate-based heuristic algorithm is proposed, which can get ≤1.5 approximation ratio under different workload scenarios and achieve at least 1.7 times as much service acceptance ratio as the baseline approach.

We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random num- ber generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.

Hardware security concerns such as intellectual property (IP) piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this article, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Security, for the first time, will be treated as one design metric for emerging nano-architecture. Five example circuit structures including camouflaging gates, polymorphic gates, current/voltage-based circuit protectors, and current-based XOR logic are designed to show the high efficiency of silicon nanowire FETs and graphene SymFET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of non-CMOS devices.

Source degeneration of access devices in the parallel (P)_ anti-parallel (AP) switching in Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) has ultimately been a limiting factor in the operational speed of these types of memories. In this work, new architectures for memory single-cells and arrays of cells are presented that utilize Schottky-Barrier Silicon Nanowire Field Effect Transistors with polarity control capabilities (e.g., SiNW-FETs), to substantially increase the performance of STT-MRAM, specifically Multi-Level Cell (MLC) STT-MRAM. The proposed design offers built-in reliability improvement as it omits one of the available four states in the MLC STT-MRAM memory facilitating the resistance level detection for peripheral circuitry. Our simulation results of the developed memory cell show 49.7% reductions in P-AP switching time, as well as 51.3% increases in available drive current under 1.4V supply voltage when compared to FinFET 22imi technology. With respect to memory arrays, the proposed architecture demonstrates an average write latency reduction of 37% in comparison with FinFET 22nm technology node.

Hardware security concerns such as IP piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this paper, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Three example circuit structures including camouflaging gates, polymorphic gates and power regulators are designed to prove the high efficiency of silicon nanowire FETs and graphene Sym FET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of emerging technologies.

This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design.

This paper proposes a highly efficient methodology for the statistical analysis of RC nets subject to manufacturing variabilities, based on the combination of parameterized RC extraction and structure-preserving parameterized model order reduction methods. The sensitivity-based layout-to-circuit extraction generates first-order Taylor series approximations of resistances and capacitances with respect to multiple geometric parameter variations. This formulation becomes the input of the parameterized model order reduction, which exploits the explicit parameter dependence to produce a linear combination of multiple non-parameterized transfer functions weighted by the parameter variations. Such a formulation enables a fast computation of statistical properties such as the standard deviation of the transfer function given the process spreads of the technology. Both the extraction and the reduction techniques avoid any parameter sampling. Therefore, the proposed method achieves a significant speed up compared to the Monte Carlo approaches.

To help promote more widespread adoption of hardware acceleration in parallel scientific computing we present portable, flexible design components for pseudorandom number generation. Due to the success of the Scalable Parallel Random Number Generators (SPRNG) software library in stochastic computations (e.g., Monte Carlo simulations), we developed an efficient and portable hardware architecture fully compatible with SPRNG's Parallel Additive Lagged Fibonacci Generator (PALFG). Our general design produces identical results for all the parameter sets that SPRNG supports and yields high performance parallel random number generators, which can each generate 162 million 31 bit uniform random integers per second on Xilinx Virtex II Pro FPGAs. The friendly design interface makes it easy for users to integrate into their applications, particularly computational scientists unfamiliar with reconfigurable hardware. Due to its fast generation speed and friendly interface, this uniform random number generator is being targeted as an open core for parallel scientific computing.