The rapid development of artificial intelligence (AI) systems has engendered a considerable increase in the computational power required in data-intensive applications, including facial recognition and image processing applications. The conventional von Neumann architecture, in which large quantities of data are transmitted between processing units and memory units, creates a bottleneck in AI applications. In-memory computing (IMC) offers an efficient solution to this problem by enabling computations within memory units, thus reducing the need for data transmission. This paper proposes a multilogic sense amplifier (MSA) with a dynamic reference voltage (DRV) generation circuit (hereafter denoted as MSA-DRV) to enhance the performance and reduce the power consumption of static random-access memory (SRAM)-based IMC. The proposed MSA-DRV performs six logic operations, namely the AND, NAND, OR, NOR, XOR, and XNOR operations, within an SRAM array by using a novel DRV circuit. The DRV circuit enables the voltage threshold to be adaptively changed according to the requirements of different operations. Experimental results indicated that the proposed MSA-DRV had lower computational latency (on average 29.9% lower) and power consumption (on average 30.6% lower) than did a conventional sense amplifier design and reconfigurable assist sense amplifier. Thus, the proposed design can overcome the von Neumann bottleneck to facilitate high-speed, energy-efficient data processing, which is crucial for AI-based and other data-intensive applications.

Approximate computing is an efficient approach for reducing computational costs. This method involves a trade-off between computational accuracy and the circuit's power consumption, delay, and area. However, the accuracy requirements may differ for different applications. In some situations, precise results are required. Therefore, this paper proposes an accuracy-configurable radix-4 adder (ACRA), which uses the power gating technique to turn on or turn off the partial logic gates of an adder element dynamically to compute accurate or approximate results. When the ACRA operates in the approximate mode, the partial sum of one adder element is modified to reduce the error distance between the approximate and accurate results. A comparison of the ACRA with two state-of-the-art accuracy-configurable adders indicated that the ACRA achieved the best trade-off between the power-delay product and computational accuracy. In addition, in the image processing experiment conducted in this study, under half-approximate computation, the peak signal-to-noise ratio of the ACRA was less than 1 dB and its structural similarity index measure was maintained above 0.99. These results are superior to those obtained for other accuracy-configurable adders.

In this paper, we design an enhanced access network discovery and selection function (ANDSF), named E-ANDSF, which provides previous mobile access gateway (PMAG) with information for base station selection, and propose an improved IP-based handover/offload scheme, calledIP-basedHandover/offload system assisted byE-ANDSF (IHEAD), which invokes multilayer perceptron, a machine learning technique, to select a base station for user equipment to handover or offload network traffic to wireless local area network (WLAN). The purpose is improving network service quality with the assistance of stream control transmission protocol and E-ANDSF. Experimental results show that the IHEAD outperforms those tested schemes.

Network-on-Chip (NoC) is an efficient on-chip communication architecture specifically for System-on-a-Chip (SoC) design. However, the input buffers of a NoC router often take a significant portion of the silicon area and power consumption. Besides, the performance of a NoC is also greatly affected by the buffer size. In this article, a static buffer merging and resource sharing method is proposed for the application-specific SoC minimizing the NoC buffer. When given an application-specific task graph and the dataflow distribution, the proposed method statically merges rarely used buffers and generates the suitable number of input buffers for each router at design timely. The merged buffer is shared by several input directions. The experimental result shows that the buffer can be utilized more effectively after the resource sharing. Based on the synthesized design with TSMC 90nm technology, the proposed method reduces an average of 42.23% area and 35.13% power while providing similar performance.

Network-on-Chip (NoC) is an on-chip communication method with good scalability and reliability. One of the most important issues of NoC design is low transmission latency design. In this paper, we propose a priority based output arbitration method to eliminate the congestion state of the NoC. By detecting and dispatching the packet requirements from different directions, the packets have different priorities. According to the priorities, the packets can pass the congested router in order. Simulation results demonstrate that the proposed method can reduce the transmission latency about 20% in uniformly distributed traffic and about 30% in hot-spot traffic when compare with the conventional router. In the router design, the new arbiter area overhead is less than 1%.

In this paper, a novel fuzzy modeling method is developed for a class of nonlinear system. The idea comes from the concepts of the Takagi-Sugeno (T-S) fuzzy modeling technique, and this method is especially suitable for the nonaffine nonlinear system. Firstly, an inverted pendulum mounted on motor-driven cart is illustrated to demonstrate the validity of modeling result. Besides this example, a nonaffine nonlinear system is illustrated to explain the proposed modeling scheme is more suitable to model the nonaffine nonlinear system into a T-S fuzzy system than some conventional fuzzy modeling schemes.

In modern Network-on-Chip (NoC) design, how to guarantee the data correctness from source IP to destination IP becomes an important issue. Error detection can be one of the solutions of this problem. In this paper, a distinguishable error detection method and the corresponding router are proposed to solve the data correctness problem. In the proposed method, the significant or critical data will be checked strictly while the other data will be checked slightly. Simulation results demonstrate that the proposed method not only provides an effective error detection scheme but also has better power-delay product than conventional technique.

This paper presents robust fuzzy controllers for a class of T-S time-delay discrete fuzzy bilinear systems (DFBSs) with disturbance which ensures the robust asymptotic stability of the closed-loop system and guarantees an Hinfinnorm bound constraint on disturbance attenuation. Firstly, we proposed a Hinfinfuzzy controller to stabilize the T-S DFBS with disturbance. Secondly, based on the Schur complement and some variable transformation, the stability conditions of the overall fuzzy control system are formulated by linear matrix inequalities (LMIs). Finally, the validity and applicability of the proposed schemes are demonstrated by simulations.

In this paper, we propose a method to solve the multiple supply voltage scheduling problem which is to assign the operational nodes of a control/data flow graph to a voltage level to minimize the average power consumption within a given computation time. Different from the previous researches focused on the operational nodes in the critical path and utilized the slack time to change the voltage of other nodes, our method can deal with all nodes without considering whether the node is in the critical path or not, and the benefit is that the voltage assignment of each node becomes more flexible. The proposed method consists of two phases, the scheduling phase and the adjusting phase, and considers both the power (delay) of the computational components and the power (delay) of the level shifters. Experimental result shows that using three voltages on a number of standard benchmarks, an average power saving of 34.23% can be obtained if the delay overhead is set as 0, and 48.07% can be obtained if the total delay is set as 1.6 times of the original delay.

In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of the pipeline registers. Based on Shannon expansion, we partition a given circuit into two subcircuits such that the number of different outputs of both subcircuits are reduced, and then encode the output of both subcircuits to minimize the Hamming distance for transitions with a high switching probability. We measure the benefits of four different combinational bipartitioning and encoding architectures for comparison. The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7% for the pipeline registers and 27.1% for the total power consumption on average. To the best of our knowledge, it is the first work that presents an in-depth study on bipartition and encoding techniques to optimize power for pipelined circuits.

This paper proposes a new approach to synthesize pipelined circuits with low-power consideration. We treat each output value of a combinational circuit as one state of a finite-state machine (FSM). If the output of a combinational circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, we apply the encoding technique to the highly active subcircuit for further power reduction. In this paper, we formulate the bipartition problem and present a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Center of North Carolina (MCNC) benchmarks of 31.6% is achievable.