A novel design methodology, enabling extreme design cycle time speed up of DC - DC power converters, is developed. The concept is based on providing high accuracy post-layout RC parasitics aware results, by replacing complicated large RC netlists with small signal approximation models. Scattering parameters analysis is adopted for “on the fly” performance simulation of the power MOSFET switches' routings, which act as large passive linear networks. The RC parasitics aware back end of line (BEOL) S-parameter model is extracted and seamlessly integrated into the schematic testbench, considering the actual circuit as a black box and therefore actively cutting down the design's netlist size to minimum values. Thus, the DC – DC converter performance degradation, that previously could not be simulated, now is accurately predicted and evaluated while the respective simulation time and the number of design iterations needed from layout (physical design) to the schematic and vice versa, are minimized. The proposed methodology is validated using an Integrated Pulse Width Modulation controlled DC - DC converter product vehicle, for light energy harvesting applications, designed, simulated and fabricated in a 0.18 μm CMOS standard process. Experimental results confirm the accuracy and design cycle speed up effectiveness of the proposed novel IC power converter design methodology.

Machine learning (ML) algorithms are utilized for the implementation of a ML python-based model of dynamic behavior of Power DC – DC converters, for energy harvesting applications. This subfield of artificial intelligence, defined as the capability of a machine to imitate intelligent human behavior, is used to perform complex tasks in a way that is similar to how a designer is implementing nonlinear switching circuits, like a power DC-DC converter. The dynamic behavior of this nonlinear vehicle is simulated with ML, and in particular all the related dynamic characteristics, obtained with large signal time domain simulation, such as dynamic voltage drop – electro migration and time domain operation, are now captured rapidly with a ML approach. The related results are benchmarked versus transistor level simulations, depicting superior accuracy in minimum simulation time.

With the increasing connection of distributed energy resources, traditional energy consumers are becoming prosumers, who can both dissipate and generate energy in a smart-grid environment. This enables the wide adoption of dynamic pricing scheme, where demand and price forecast are applied for estimating energy cost and loads scheduling. Throughout this paper we propose a Peer-to-Peer (P2P) platform, as well as a light-weighted system orchestrator based on game theory to support the energy trading. Additionally, we discuss the hardware implementation of the proposed solution onto a low-cost reconfigurable device. Experimental results based on real data validate the efficiency of proposed framework, as we achieve considerable energy savings (on average cost reduction by 87%) compared to the corresponding cost from the main-grid.

A new source follower type analog buffer used as an output buffer for the data / column driver of an Active Matrix display is presented in this paper. The proposed buffer is implemented with low temperature polycrystalline silicon thin film transistor (LT poly-Si TFTs) and the main advantage of the buffer is its high immunity to the threshold voltage variation of the LT poly-Si TFTs. The functionality of the buffer is verified through simulation with HSpice, using for the simulations parameters extracted from fabricated LT poly-Si TFTs in order to obtain realistic simulation results.

Analysis concentrated on noise performance issues of a CMOS high gain second generation current conveyor (CCII∞) is presented using both simulations and measurements results. The circuit has been fabricated in a 0.35 μm CMOS process by Austria Mikro Systeme (AMS) and it is examined analytically in terms of the noise contribution of each transistor in an inverting voltage amplifier configuration. Preliminary results about the noise minimization procedure are extracted. Regarding the topology performance characteristics, the power consumption is 93 μW and the total input referred rms noise is equal to 7.03 μV for a bandwidth of 1 Hz to 100 kHz.

A comparison is made between model parameter calculation equations of RF CMOS inductors. Model parameters can be extracted from different equations using as variables either Y-, Z-parameters depending on the circuit configuration of the inductor or S-parameters. Results are based on on-wafer RF S-parameter measurements of a fabricated inductor. Differences appear between results obtained with calculation equations based on Z- and S-parameters, extracted for a differentially driven inductor. Therefore, care must be taken by the designers when evaluating an integrated inductor performance to comprehend the technological and operating environment of the device and to choose the corresponding formulas accordingly.

A simple low voltage circuit topology able to generate any positive real number power-law function is presented. The proposed circuit exploits BJTs and is based on piecewise linear approximation of the nonlinear function to be generated. An in-depth mathematical analysis is deployed. The instances of a squarer, a cube-law, a square rooting and cube rooting circuit are thoroughly examined through simulation. The obtained results verify the theoretical calculations

The influence of the light illumination on the drain current of polycrystalline silicon thin-film transistors is studied in this work. The increase of the output current as a result of raised light intensity is modeled, based on measured experimental data for different Vdsand Vgsvalues. The proposed model has been verified against the measurements and the simulated output characteristics give a good approximation in the sub-threshold region

Polysilicon thin-film technology has become of great interest due to the demand for large area electronic devices. Display applications, memories and optical copier are among the fields where polysilicon thin-film transistors (poly-Si TFTs) are most commonly used. However the design of analogue blocks, by using Poly-Si TFTs, with constant specifications is very difficult because of the large variation of the threshold voltage of the poly-Si TFT across the wafer and the kink effect makes. In this paper we propose a circuit that can sense the voltage difference between two TFTs. This voltage can be used in order to design an improved current mirror with cancellation of threshold voltage variation

The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18μm STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems.

Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

In this work, a Euclidean distance calculator is presented. The circuit comprises of simple computing blocks, their basic element being the floating gate MOSFET (FGMOS), exploiting the merits of this device in designing circuits with low-voltage and rail-to-rail operation. Therefore the overall circuit has the characteristics of modularity, low-voltage and rail-to-rail operation under a single supply voltage, accuracy and simplicity. The circuit is designed with 2/spl mu/ MIETEC CMOS technology and is used in the simulation of a hand-written digit recognition system using the nearest neighbour classification method. The simulation results presented, demonstrate the functionality of the circuit.

Simple current-mode non-linear computational circuits based on a basic cell built with floating-gate MOS transistors are proposed. The basic cell is used to construct a current square-root circuit, a current squarer and a four-quadrant current multiplier. The circuits offer large input range, low harmonic distortion and high linearity. Spice simulation results verify the performance of the proposed circuits.

In this work an analog CMOS outlier rejection circuit is proposed. The circuit calculates the instantaneous average current of an array of N analog input currents rejecting the outliers which lie outside of a desired percentage of the average current. The output of the circuit is the average current. The circuit is constructed by N identical cells which select the low and high outliers and an average circuit. The circuit finds many applications in parallel processing of the miniaturized sensor array signals.