This paper addresses the problem of assessing the effect of communication delays on the control performance of a platoon of two vehicles. We consider Bluetooth communication and develop a simple stochastic model for the Bluetooth delay distribution. It is shown that due to the long tails of this distribution, the computation time of a Monte Carlo approach would be prohibitive when assessing the effect of long communication delays on the control performance. Hence, we propose a novel and fast simulation approach that is computationally more efficient than pure Monte Carlo simulations. Simulations on a platoon of two vehicles illustrate the effectiveness of the approach for assessing average and worst case performance or for approximating the probability density function of the control performance.

Quality-Energy scalability has been proved to be an effective technique toward the cost reduction for signal processing. However, although it has large potentials for reducing signal processing energy in wireless transceivers, it has not yet been applied to them. In this paper, we elaborate an example and present a feedback control scheme to achieve Quality-Energy scalability for the chip level equalization in High Speed Downlink Packet Access (HSDPA) receivers. In conventional equalizers, the coefficients are updated according to the worst-case assumption that the channel is very dynamic. In our proposed approach, we take into account the speed of the channel variation to adapt the updating frequency. Specifically, a low-complexity closed-loop controller is designed to vary the update-interval while limiting the maximum equalization error. The proposed control scheme takes high order channel statistics implicitly into account without the need for an explicit estimator. Simulation results show that the Quality-Energy scalability for the equalizer results in significant energy reduction with minor quality degradation for channels with large coherence times. Specifically, for a pedestrian channel, 60% of the signal processing operations, and hence energy, can be saved with only 0.25 dBBERloss.

Nowadays, a lot of effort is spent on developing inexpensive orthogonal frequency-division multiplexing (OFDM) receivers. Especially, zero intermediate frequency (zero-IF) receivers are very appealing, because they avoid costly IF filters. However, zero-IF front-ends also introduce significant additional front-end distortion, such as IQ imbalance. Moreover, zero-IF does not solve the phase noise problem. Unfortunately, OFDM is very sensitive to the receiver nonidealities IQ imbalance and phase noise. Therefore, we developed a new estimation/compensation scheme to jointly combat the IQ imbalance and phase noise at baseband. In this letter, we describe the algorithms and present the performance results. Our compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. The compensation scheme has a fast convergence and a small residual degradation: even for large IQ imbalance, the overall system performance for an OFDM-wireless local area network (WLAN) case study is within 0.6 dB of the optimal case. As such, our approach greatly relaxes the mismatch specifications and thus enables low-cost zero-IF receivers.

Zero-IF receivers are gaining interest because they enable low-cost WLAN OFDM terminals. However, zero-IF receivers introduce IQ imbalance which may have a huge impact on performance. Rather than increasing component cost to decrease the IQ imbalance, an alternative is to tolerate the IQ imbalance and compensate it digitally. Current solutions converge too slowly for bursty WLAN communication. Moreover, the tremendous impact of a frequency offset on the IQ estimation/compensation problem is not considered. We analyze joint IQ-CFO estimation/compensation and propose a low-cost, highly effective compensation scheme. For large IQ imbalance (/spl epsi/=10%, /spl Delta//spl phi/=10/spl deg/) and large frequency offset, our solution results in an average remaining degradation below 0.5 dB compared to the reference case without IQ imbalance or frequency offset. It therefore enables the design of low-cost, low-complexity WLAN OFDM receivers.

Today a lot of attention is spent on developing inexpensive OFDM receivers. Especially, zero-IF receivers are very appealing, because they avoid costly IF filters. However, this implies IQ demodulation at RF, which therefore cannot be done digitally and thus introduces IQ mismatch. Unfortunately, OFDM is very sensitive to receiver IQ imbalance. Therefore, we developed a new compensation scheme to combat the IQ imbalance at baseband. In this paper, we describe the algorithm and represent the performance results. Our compensation scheme eliminates the IQ imbalance almost perfect. This leads to tremendous improvements, especially in multi-path channels (up to 10 dB performance gain), and enables low-cost zero-IF receivers.

There is an ongoing discussion in the broadband wireless world between OFDM and single-carrier. Single-carrier allows for more relaxed front-end requirements. OFDM, on the other hand, can yield better performance at low complexity. Recently, a new single-carrier scheme with frequency domain equalization and decision-feedback has been proposed for a SISO channel. This single-carrier scheme can reach the OFDM performance. We extend this new scheme for multiple antennas and multiple users. We show that this multi-user scheme with decision-feedback has a 3 dB gain over conventional linear single-carrier multi-user schemes and still maintains a low complexity. We illustrate that our scheme is equivalent with the generalized decision-feedback equalizer, but has a lower complexity.

The combination of space-time block coding (STBC) and direct-sequence code-division multiple access (DS-CDMA) has the potential to increase the performance of multiple users in a cellular network. However, if not carefully designed, the resulting transmission scheme suffers from increased multiuser interference (MUI), which dramatically deteriorates the performance. To tackle this MUI problem in the downlink, we combine two specific DS-CDMA and STBC techniques, namely single-carrier block transmission (SCBT) DS-CDMA and time-reversal STBC. The resulting transmission scheme allows for deterministic maximum-likelihood (ML) user separation through low-complexity code-matched filtering, as well as deterministic ML transmit stream separation through linear processing. Moreover, it can achieve maximum diversity gains of N/sub T/N/sub R/(L+1) for every user in the system, irrespective of the system load, where N/sub T/ is the number of transmit antennas, N/sub R/ the number of receive antennas, and L the order of the underlying multipath channels. In addition, it turns out that a low-complexity linear receiver based on frequency-domain equalization comes close to extracting the full diversity in reduced, as well as full load settings. In this perspective, we also develop two (recursive) least squares methods for direct equalizer design. Simulation results demonstrate the outstanding performance of the proposed transceiver compared to competing alternatives.

Orthogonal frequency-division multiplexing with cyclic prefix enables low-cost frequency-domain mitigation of multipath distortion. However, to determine the equalizer coefficients, knowledge of the channel frequency response is required. While a straightforward approach is to measure the response to a known pilot symbol sequence, existing literature reports a significant performance gain when exploiting the frequency correlation properties of the channel. Expressing this correlation by the finite delay spread, we build a deterministic model parametrized by the channel impulse response and, based on this model, derive the maximum-likelihood channel estimator. In addition to being optimal (up to the modeling error), this estimator receives an elegant time-frequency interpretation. As a result, it has a significantly lower complexity than previously published methods.

The two major obstacles toward high-capacity indoor wireless networks are distortion due to the indoor channel and the limited bandwidth which necessitates a high spectral efficiency. A combined orthogonal frequency division multiplexing (OFDM)/spatial division multiple access (SDMA) approach can efficiently tackle both obstacles and paves the way for cheap, high-capacity wireless indoor networks. The channel distortion due to multipath propagation is efficiently mitigated with OFDM while the bandwidth efficiency can be increased with the use of SDMA. However, to keep the cost of an indoor wireless network comparable to its wired counterpart's cost, low-complexity SDMA processors with good performance are of special interest. In this paper, we propose a new multiuser SDMA detector which is designed for constant modulus signals. This constrained least squares (CLS) receiver, which deterministically exploits the constant modulus nature of the subcarrier modulation to achieve better separation, is compared in terms of performance and complexity with the zero forcing (ZF) and the minimum mean square error (MMSE) receiver. Additionally, since the CLS detector relies on reliable channel knowledge at the receiver, we propose a strategy for estimating the multiple input multiple output (MIMO) channels. Simulations for a Hiperlan II-based case-study show that the CLS detector significantly outperforms the ZF detector and comes close to the performance of the MMSE detector for QPSK. For higher order M-PSK, the CLS detector outperforms the MMSF detector. Furthermore, the estimation complexity for the CLS detector is substantially lower than that for the MMSE detector which additionally requires estimation of the noise power.

In this paper, we extend space-time block coding techniques, originally proposed for point-to-point communication links, to point-to-multipoint communication links, thereby taking into account the multiple access technique in the design of the transmission scheme. In specific, we propose two per-tone linear space-time chip equalizers for a space-time coded MC-DS-CDMA downlink with linear precoding. Both the training-based and the semi-blind chip equalizer exploit the presence of a continuous code-multiplexed pilot in the transmitted signal but differ in the amount of a-priori information they assume to estimate their coefficients. With Mttransmit antennas at the base-station, Mrreceive antennas at the mobile station and L the order of the multipath channel, they come close to extracting the full diversity of order Mt· Mr· (L + 1) in reduced as well as full load settings.

In the downlink of WCDMA systems, multi-path propagation destroys the orthogonality of the user signals and causes multi-user interference (MUI). Chip-level equalization can restore the orthogonality and suppress the MUI. However, adaptive implementations of the chip-level equalizer receiver that can track time-varying multi-path channels are hard to realize in practice for two reasons: loss of spectral efficiency when using a training sequence and loss of performance when using pure blind techniques. We propose new training-based and semi-blind space-time chip-level equalizer receivers for the downlink of WCDMA systems employing long spreading codes and a continuous code-multiplexed pilot. The proposed receivers exploit the presence of common pilot symbols in the so-called Common PIlot CHannel (CPICH) of the Universal Terrestrial Radio Access (UTRA) for 3G systems. Moreover, they can simultaneously track multiple base-station signals, whenever the mobile station enters soft handover mode. For both receivers, we derive a recursive least squares (RLS) algorithm for adaptive processing. The proposed receivers are compared with the conventional space-time RAKE receiver and the ideal space-time chip-level equalizer receiver both in terms of performance and complexity.

The two major obstacles toward high-capacity indoor wireless networks are distortion due to the indoor channel and the limited availability of bandwidth which necessitates a high spectral efficiency. A combined orthogonal-frequency division multiplexing/spatial-diversity multiple access (OFDM/SDMA) approach can effectively tackle both obstacles. The channel distortion due to multipath propagation is easily mitigated with OFDM while the bandwidth efficiency can be increased with the use of SDMA. In order to keep the network's cost acceptable, simplified SDMA processors are preferred over the exponentially complex optimal maximum-likelihood processors. However, these simplified processors perform significantly worse than the optimal ones in terms of average bit error rate (BER). In this paper, we show that by adapting the constellation sizes applied on the individual subcarriers to the channel conditions, the performance of OFDM/SDMA processors can be significantly enhanced. In the uplink, we derive simple closed-form equations for the optimal constellation sizes for both a simple linear minimum mean-square error (MMSE) detector and for a nonlinear MMSE decision feedback equalizer (DFE) detector. Furthermore, for each detector, we introduce a simplified loading algorithm which lowers the computational and signaling complexity substantially at a small performance penalty. In the downlink, we study the dual precoders of the uplink detectors, respectively, the linear MMSE precoder and the nonlinear Tomlinson-Harashima (TH) MMSE-based precoder. For both precoders, we derive expressions for the optimal and the simplified constellation sizes. Additionally, we show that in time-division duplexing systems, the constellation distribution of a set of dual detectors/precoders is identical for up- and downlink, which effectively halves the computational complexity of adaptive loading. In the fully loaded uplink, the proposed adaptive loading algorithm results in a gain of 9 dB for a BER=10/sup -3/ for the linear MMSE detector and a gain of 4.5 dB for the nonlinear MMSE-DFE detector. In the fully loaded downlink, a gain of 6.3 dB is achieved for the MMSE precoder and 5.5 dB for the TH-MMSE precoder.

A virtual interface between Java and FPGA for networked reconfiguration is presented. Through the Java/FPGA interface, Java applications can exploit hardware accelerators with FPGAs for both functional flexibility and performance acceleration. At the same time, the interface is platform independent. It enables the networked application developers to design their applications with only one interface in mind when considering the interfacing issues. The virtual interface is part of our work to build a platform-independent deployment framework for the networked services. In the framework, both the software and hardware components of services can be platform independently described and deployed.

Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract the model of the substrate from the layout information and then simulate the extracted transistor-level netlist with this substrate model using a transistor-level simulator. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator. In our previous work, it has been demonstrated that efficient and accurate simulation of substrate noise generation at gate-level is feasible. In this paper several important extensions to our previous work are introduced: modeling of I/O cells, modeling of input transition time and load dependency and the extraction methodology of an equivalent substrate model within multiple supply domains. Experimental results show an improved accuracy (6.3% error on RMS substrate voltage with respect to a full SPICE level simulation) with these extensions, while maintaining a large speedup with respect to SPICE simulations.

Multicarrier modulation schemes are widely used in several digital telecommunication systems, such as Asymmetric Digital Subscriber Lines (ADSL) and Wireless Local Area Network (WLAN) based on Orthogonal Frequency Domain Multiplexing (OFDM). An estimate of the Bit-Error-Rate (BER) degradation due to non-idealities in the transceiver (e.g. nonlinear distortions in the analog front-ends, digital clipping,...) is much more complicated in a multicarrier system than in a single-carrier system due to the large number of carriers and the huge number of possible transmitted symbols. This paper proposes a method for estimating the BER of such OFDM modulation schemes in a CPU time that is two orders of magnitude smaller than a Monte-Carlo method, as confirmed by simulations on a 5 GHz IEEE 802.11 WLAN receiver front-end.

In the downlink of WCDMA systems, multipath propagation destroys the orthogonality of the user signals and causes multi-user interference (MUI). Chip-level equalization can restore the orthogonality and suppress the MUI. However, adaptive implementations of the chip equalizer receiver that can track time-varying multipath channels are hard to realize in practice. In this paper, we propose new training-based and semi-blind space-time chip equalizer receivers for the downlink of WCDMA systems employing long spreading codes and a code-multiplexed pilot. The proposed receivers exploit the presence of common pilot symbols in the so-called Common Pilot Channel (CPICH) of the Universal Terrestrial Radio Access (UTRA) for 3G systems. Moreover, they can simultaneously track multiple base-station signals, whenever the mobile station enters soft handover mode. For both receivers, we derive a Least Squares algorithm for block processing and a Recursive Least Squares algorithm for adaptive processing. The proposed receivers are compared in terms of performance with the conventional space-time RAKE receiver and the ideal fully-trained space-time chip equalizer receiver.

Link adaptation (LA) can significantly increase the spectral efficiency and render various levels of services, both of which are highly desirable for today's high-speed communication systems. Although optimality can be ensured through careful designing for a fixed link configuration, due to changes of available power, data rate, and especially channel statistics, it is better to adapt the adaptation scheme per se in real time. We term this technique adaptive link adaptation (ALA). Based on our previous work on a general optimal link adaptation scheme for a certain configuration, we continue to investigate the problem of adapting the adaptation scheme online. This paper first recapitulates that general optimal link adaptation scheme, then gives the theoretic basis of ALA, and finally presents a simple yet working implementation of the update algorithm for ALA. Both theoretical and simulation results indicate the viability of ALA and an 18 dB gain can be achieved for the investigated simple scenario. With low complexity, optimality, and generality, the proposed ALA provides a promising technique to substantially increase the spectral efficiency of practical communication systems.

The two major obstacles towards high-capacity indoor wireless networks are distortion due to the indoor channel and the limited bandwidth. A combined OFDM/SDMA approach efficiently tackles both obstacles and paves the way for low cost, high-capacity wireless indoor networks (see Vandenameele, P. et al., VTC Spring, p.1712-16, 1999; IEEE J. Selected Areas in Commun., vol.18, no.11, p.2312-21, 2000). Channel distortion due to multipath propagation is efficiently mitigated by orthogonal frequency division multiplexing (OFDM) while the bandwidth efficiency is increased by the use of spatial diversity multiple access (SDMA). To keep the WLAN cost low, simple SDMA processors with good performance are necessary. Hence, we propose a new, low-complexity multiuser SDMA detector, which is designed for constant modulus signals. This linear constrained least squares (CLS) receiver, which explicitly exploits the constant modulus nature of subcarrier modulation to achieve better separation, is compared in terms of performance and complexity with the zero forcing (ZF) and the minimum mean square error (MMSE) receivers. Simulations show that the CLS detector significantly outperforms the ZF detector and comes close to the performance of the MMSE detector for QPSK. For higher order MPSK, the CLS detector outperforms the MMSE detector substantially.

In the forward link of WCDMA systems, the multipath propagation channel destroys the orthogonality of the spreading codes and therefore causes multi-user interference (MUI). We propose new training-based and semi-blind space-time chip equalizer receivers for the forward link of WCDMA systems with a continuous code-multiplexed pilot. Both least-squares (LS) algorithms for block processing and recursive least-squares (RLS) algorithms for adaptive processing are derived. The proposed receivers can track fast fading multipath channels and outperform the RAKE receiver with perfect channel knowledge.

Orthogonal frequency-division multiplexing (OFDM) with cyclic prefix enables low cost frequency-domain mitigation of multipath distortion. However, to determine the equalizer coefficients, knowledge of the channel frequency response is required. While a straightforward approach is to measure the response to a known pilot symbol sequence, existing literature reports a significant performance gain when exploiting the frequency correlation properties of the channel. Expressing this correlation by the finite delay spread, we build a deterministic model parametrized by the channel impulse response and, based on this model, derive the maximum likelihood (ML) channel estimator. In addition to being optimal, this estimator receives an elegant time-frequency interpretation. As a result, it has a significantly lower complexity than previously published methods.

Future broadband satellite systems, supporting user terminal mobility, will employ regenerative LEO satellites with multiple spot-beams per satellite. MC-CDMA is a promising multiple-access technique for these systems, because it exploits the advantages of both OFDM and CDMA. However, the detector design for the reverse link, taking into account both intra- and inter-beam interference, is still an open area of research. In this paper, we propose a new MC-CDMA multiuser detector, that can deal with both intra- and inter-beam interference in frequency-selective fading channels. The ideal detector consists of an initial linear MMSE stage and possibly multiple nonlinear pcPIC-MMSE stages, that act on a per-carrier basis. Furthermore, to take care of its initialisation, we devised a training-based fully adaptive detector, that does not require any a priori information and achieves the same steady-state performance as the ideal detector. The MMSE/pcPIC-MMSE detector outperforms a classical MMSE detector by 4 dB for a BER of 10/sup -2/, while still maintaining linear complexity in the number of users.

In the forward link of WCDMA systems, multipath propagation destroys the orthogonality of the user signals and causes multi-user interference (MUI). Channel equalization can restore the orthogonality and suppress the MUI. However, adaptive implementations of the chip equalizer receiver that can track time-varying multipath channels are hard to realize in practice. In this paper, we propose new training-based and semi-blind space-time chip equalizer receivers for the forward link of WCDMA systems employing long spreading codes and a time-multiplexed pilot. The proposed receivers exploit the presence of user specific pilot symbols in the so-called dedicated physical control channel (DPCCH) of the Universal Terrestrial Radio Access (UTRA). Whereas the DPCCH-trained receiver only assumes knowledge of the desired user's pilot symbols and code sequence in a training-based cost function, the enhanced DPCCH-trained receiver assumes knowledge of each active user's pilot symbols and code sequence in a semi-blind cost function. For both receivers, we derive a least squares algorithm for block processing and a recursive least squares algorithm for adaptive processing. Both receivers can track time-varying multipath channels and outperform the conventional RAKE receiver with perfect channel knowledge. The enhanced DPCCH-trained chip equalizer receiver outperforms the regular DPCCH-trained chip equalizer receiver and comes close to the performance of the ideal fully-trained chip equalizer receiver.

Link adaptation (LA) can significantly increase the spectral efficiency and meantime provide services of various qualities, both of which are highly desirable in today's high-speed communication systems. However how to perform precise switching optimally in practical systems involving non-flat fading channels and several adaptive techniques is seldom treated. We therefore investigate this problem and propose a general optimal switching scheme. This paper gives a framework of such a scheme for link adaptation and a detailed designing procedure. We present a vigorous proof of the optimality condition and show that the optimal switching boundaries have a linear relationship, which is independent of coding, modulation and channels. Also, we extend this scheme to multicarrier, MIMO and multiservice systems to ensure global optimality. With low complexity, optimality, and generality the proposed general optimal switching scheme provides a promising technique to substantially increase the spectral efficiency of practical communication systems.

The two major obstacles towards high-capacity indoor wireless networks are distortion due to the indoor channel and the limited bandwidth which necessitates a high spectral efficiency. The combination of single carrier with cyclic prefix (SC-CP) modulation and spatial division multiple access (SDMA) tackles both obstacles and paves the way for low cost, high-capacity wireless indoor networks (see Vandenameele, P. et al., ICASSP, p.3714-17, 2000). The channel distortion due to multipath propagation is elegantly mitigated with SC-CP while the bandwidth efficiency is increased with the use of SDMA. However, to keep the WLAN cost low, simple SDMA processors with good performance are necessary. Hence, we propose a new low-complexity multiuser SDMA detector, which is designed for constant modulus signals. This linear constrained least squares (CLS) receiver, which explicitly exploits the constant modulus nature of the modulation, is compared in terms of performance and complexity with the zero forcing (ZF) and the minimum mean square error (MMSE) receiver. Simulations show that the CLS detector significantly outperforms the ZF detector and comes very close to the performance of the MMSE detector. Furthermore, the estimation complexity for the CLS detector is substantially lower than for the MMSE detector, which additionally requires estimation of the noise power.

In recent years, wireless indoor networks have received a lot of scientific and industrial attention. Most systems rely on the use of orthogonal frequency division multiplexing (OFDM) because of its capability to elegantly cope with multipath interference. However, while OFDM provides a nice solution for the digital modem, its front-end requirements should be investigated as well. To that goal, we have set up a simulation environment which comprises both the digital modem and the most important front-end nonidealities. We show that for the same data rate, bandwidth and transmit power constraints, Single-Carrier with Cyclic Prefix (SC-CP) allows the design of a more power-efficient modem than OFDM and is therefore a better candidate for portable wireless terminals.

The average bit-error rate of transmit antenna selection combined with receive maximum-ratio combining is computed as a function of the transmit antenna update rate when using binary phase-shift keying in flat Rayleigh fading channels. This scheme achieves an order of diversity equal to the product of the number of transmit and receive antennas. Therefore, it can gain significant diversity benefits over traditional receive diversity schemes by distributing the antennas over the transmit and receive side.

Turbo codes are the most recent breakthrough in coding theory. However, the decoder's implementation cost limits their incorporation in commercial systems. Although the decoding algorithm is highly data dominated, no true memory optimization study has been performed yet. We have extensively and systematically investigated different memory optimizations for the maximum a posteriori (MAP) class of decoding algorithms. It turns out that it is not possible to present one decoder structure as being optimal. In fact, there are several tradeoffs, which depend on the specific turbo code, the implementation target (hardware or software), and the selected cost function. We therefore end up with a parametric family of new optimized algorithms out of which the designer can choose. The impact of our optimizations is illustrated by a representative example, which shows a significant decrease in both decoding energy (factor 2.5) and delay (factor 1.7).

Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

The design of analog front-ends of digital telecommunication transceivers requires simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom-up model of nonlinear analog continuous-time circuits used in communication systems. The models take into account frequency dependence of the nonlinear behavior, making them suitable for wideband applications. Such model consists of a block diagram that corresponds to the most important contributions to the second- and third-order Volterra kernels of the output quantity (voltage or current) of a circuit. The examples in this paper, a high-level model of a CMOS low-noise amplifier and an active lowpass filter, demonstrate that the generated models can be efficiently evaluated in high-level dataflow-type simulations of mixed-signal front-ends and that they yield insight in the nonlinear behavior of the analog front-end blocks.

Frequency domain equalization has gained a lot of attention in the last decade, mainly pushed by the OFDM (orthogonal frequency division multiplexing) communication scheme. It has been adopted, in various flavours, for, among others, wireless LANs and xDSL. The technique is indeed leading to low complexity implementation, at the cost of a cyclic prefix, used to avoid inter block interference (IBI). The idea has been adapted to single carrier communication, almost "as is", yielding the same computational advantages and avoiding the high crest factor of OFDM. We name this scheme CP-SC (cyclic prefix-single carrier). We take a new look at this single carrier scheme, and, with a slight modification, show that the cyclic prefix can be implemented as a training sequence, and hence play two important roles: avoid IBI and help in synchronisation and channel estimation. The latter topic is of utter importance in fast fading situations (e.g. mobile). This new training aided frequency domain equalized single carrier (we name it TASC) scheme offers these advantages at the expense of only a small fraction of a dB (in terms of E/sub b//N/sub 0/). All these arguments make TASC an interesting candidate in situations where multipath and fast fading are present, while in other situations it has hardly no drawback compared to CP-SC.

The combination of orthogonal frequency division multiplexing (OFDM) with linear processing-based spatial diversity multiple access (SDMA) enables high-capacity wireless local networks at reasonable implementation complexity. We investigate adaptive loading of the carriers as a means for lowering the relatively high symbol error rate (SER) of such linear OFDM/SDMA networks and propose efficient closed-form expressions for the optimal bit distributions. We analyze the performance and complexity of the proposed algorithms and show that substantial gains in SER can be achieved. Furthermore, simplified algorithms are proposed which have a small performance penalty but which possess a lower computational and signaling cost.

Two major technical challenges in the design of future broadband wireless networks are the impairments of the propagation channel and the need for spectral efficiency. We previously proposed a combined OFDM/SDMA approach that mitigates the channel impairments by orthogonal frequency division multiplexing (OFDM) with cyclic prefix insertion and that achieves a high spectral efficiency by space division multiple access (SDMA). However, because of the multicarrier modulation, this approach requires high-backoff power amplifiers in the analog frontend. We present a SC-FD-SDMA basestation, which avoids these expensive amplifiers by using constant-envelope single-carrier (SC) modulation and still features the advantages of frequency-domain (FD) multipath mitigation and SDMA. We pay special attention to the initialization of such basestation and its fixed point requirements, since they are critical aspects of any realistic implementation. A case-study shows how SC-FD-SDMA enables a 100 Mbps wireless LAN with a bandwidth efficiency of 8 bps/Hz and an uncoded BER of 10/sup -3/ at 13.5 dB.

Two major technical challenges in the design of future broadband wireless networks are the impairments of the propagation channel and the need for spectral efficiency. To mitigate the channel impairments, orthogonal frequency division multiplexing (OFDM) can be used, which transforms a frequency-selective channel in a set of frequency-flat channels. On the other hand, to achieve higher spectral efficiency, space division multiple access (SDMA) can be used, which reuses bandwidth by multiplexing signals based on their spatial signature. In this paper, we present a combined OFDM/SDMA approach that couples the capabilities of the two techniques to tackle both challenges at once. We propose four algorithms, ranging from a low-complexity linear minimum mean squared error (MMSE) solution to the optimal maximum likelihood (ML) detector. By applying per-carrier successive interference cancellation (pcSIC), initially proposed for DS-CDMA, and introducing selective state insertion (SI), we achieve a good tradeoff between performance and complexity. A case study demonstrates that, compared to the MMSE approach, our pcSIC-SI-OFDM/SDMA algorithm obtains a performance gain of 10 dB for a BER of 10/sup -3/, while it is only three times more complex. On the other hand, it is two orders of magnitude less complex than the ML approach, for a performance penalty of only 2 dB.

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The "system-on-a-package" approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications.

A fully digital QAM16 burst receiver ASIC is presented.The B04 receiver demodulates at 10 Mbit/s and uses an advanced signal processing architecture that performs perburst automatic equalization.It is a critical building block in a broadband access system for HFC networks.The chip was designed using a C++ based flow and is implemented as a 80 Kgate 0.7~ CMOS standard cell design.

Standard interfaces for hardware reuse are currently defined at the structural level.In contrast to this, our contribution defines the reuse interface at the behavioral registertransfer (RT) level.This promotes direct reuse of functionality and avoids the integration problems of structural reuse.We present an object oriented reuse interface in C++ and show the use of it within two real-life designs.

Although a single-chip solution seems to be ultimate goal for the design of wireless transceivers, there are many reasons to believe that this approach is not feasible for high performance applications. Especially the RF front-ends of these transceivers require components that are difficult to combine into one single chip. As an alternative we propose a single-package solution that contains different components that are interconnected with a multi-chip module (MCM) interconnect technology. By implementing passive front-end components directly into this interconnect technology, instead of using external commercial components, a cost-effective realization of the front-end can be obtained with a higher performance or a lower power consumption.

Turbo codes are the most recent breakthrough in coding theory.Although their decoding algorithm is highly data dominated, no systematic memory optimization study has been performed yet.We have applied the IMEC Data Transfer and Storage Exploration (DTSE) methodology to the MAP (Maximum A Posteriori) class of turbo decoding algorithms.We present an extensive overview of our optimizations and tradeoffs, which result in a parametric family of new optimized algorithms.The optimal choice of parameters depends on the specific turbo code and on the implementation target, which can be either hardware or software.

This paper addresses the problem of minimizing memory size and memory accesses in multiresolution texture coding architectures for discrete cosine transform (DCT) and wavelet-based schemes used, for example, in virtual-world walk-throughs or facial animation scenes of an MPEG-4 system. The problem of minimizing the memory cost is important since memory accesses, memory bandwidth limitations, and in general the correct handling of the data flows have become the true critical issues in designing high-speed and low-power video-processing architectures and in efficiently using multimedia processors. For instance, the straightforward implementation of a multiresolution texture codec typically needs an extra memory buffer of the same size as the image to be encoded/decoded. We propose a new calculation schedule that reduces this buffer memory size with up to two orders of magnitude, while still ensuring a number of external (off-chip) memory accesses that is very close to the theoretical minimum. The analysis is generic and is therefore useful for both wavelet and multiresolution DCT codecs.

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are essen tial for the design of such a complex system. It is sho wn how a C++ programming approach outperforms traditional HDL-based methods.

The upcoming multimedia processing applications will require high memory bandwidth. We estimate that a software reference implementation of an MPEG-4 video decoder typically requires 200 Mtransfers/s to memory to decode 1 CIF (352/spl times/288) video object plane (VOP) at 30 frames/s. This imposes a high penalty in terms of power but also performance. However, we also show that we can heavily improve on the memory accesses and data transfers, without sacrificing speed (even gaining about 10% on cache misses and cycles for a DEC Alpha), by aggressive code transformations. For this purpose, we have applied an extended version of our data transfer and storage exploration methodology, partly supported in the ATOMIUM environment, which was originally developed for custom hardware implementations.

The high sample-rates involved in many DSP-applications, require the use of static schedulers wherever possible. The construction of static schedules however is classically limited to applications that fit in the synchronous data flow model. In this paper we present cyclo-static data flow as a model to describe applications with a cyclically changing behaviour. We give both a necessary and sufficient condition for the existence of a static schedule for a cyclo-static data flow graph and show how such a schedule can be constructed. The example of a video encoder is used to illustrate the importance of cyclo-static data flow for real-life DSP-systems.

We describe the rapid prototyping of a video encoder intended for transmitting compressed video data through a wireless local area network. Our work proves the feasibility of using a multiprocessor for prototyping high-data rate applications with a minimum development effort.>

In the graphical programming environment GRAPE-II intended for rapid prototyping of DSP ASICs on a multi-processor, a load balancing tool is required to map the different jobs of the DSP application on the multi-processor. Since most of the existing load balancing algorithms perform less well when they have to handle large or complex applications, the authors develop a tool that is better suited for such problems. This tool is based on three main techniques. (1) By exploiting the hierarchy that exists in the application graph, the complexity for each of the tools can be reduced. (2) Splitting the load balancing in sub tasks leads to three smaller search spaces instead of one big space. (3) Each of the smaller search spaces on its turn is reduced by using appropriate heuristic rules. As an example of this approach the scheduling tool and the basics of the assignment tool are presented.>

The second version of the graphical programming environment (GRAPE) is described. It is intended as a tool for the rapid prototyping of digital signal processing (DSP) application-specific integrated circuits (ASICs) on a multiprocessor. GRAPE-II fully supports multirate and asynchronous DSP applications and heterogeneous target multiprocessors. The extensions that are required to the programming model and the intermediate specification language to support multirate and asynchronous operation are described. The programming model is clarified by an example. The global structure of GRAPE-II is presented. The status of the project is indicated.>

The CASE tool GRAPE (GRAphical Programming Environment) is presented which allows for easy programming, compiling, debugging and evaluating high frequency real-time DSP algorithms. Its main distinctive feature is that the tool spans the whole design process, ranging from analysis over simulation and emulation up to implementation on general purpose DSP multiprocessors or integration on an Application Specific Integrated Circuit (ASIC). The DSP multiprocessor can be the target hardware or can be used for real-time emulation or accelerated simulation of an ASIC. The paper mainly focuses on the CASE tool and on the design of a flexible multiprocessor board for the real-time emulation of DSP ASIC's.>