Logic-level defects that escape manufacturing tests pose reliability risks in modern systems and require functional testing to identify their activation and propagation behaviors. However, effective functional testing is limited by the high cost of long-cycle fault simulations. To address this challenge, we propose a Spatio-Temporal Graph Convolutional Network framework to efficiently and accurately predict the Fault Impact Probability on the circuit's function cross-over multiple function cycles, enabling rapid quantitative assessment of functionally possible faults. Our method represents gate-level netlists as spatio-temporal graphs, capturing both structural connectivity and short-range signal-propagation dynamics. With dedicated spatial and temporal encoders, the proposed ST-GCN enables accurate prediction of multi-cycle circuit-level FIP. Experiments on ISCAS’89 benchmarks show that the approach reduces fault-simulation cost by over an order of magnitude while maintaining high accuracy (mean absolute error as low as 0.024 for 5-cycle predictions). The framework supports both testability-metric-based and simulation-based feature construction, enabling a tunable balance between efficiency and accuracy. A case study on test point selection further demonstrates that using predicted FIPs to guide observation-point placement improves the detectability of multi-cycle, hard-to-detect circuit-level faults. Overall, this work provides a scalable solution for circuit-level multi-cycle fault-impact assessment and can be readily integrated into functional test generation and other Electronic Design Automation workflows.

Chiplet systems that stack heterogeneous dies via 2.5D/3D integration use JTAG-based test access ports (TAPs) to validate inter-die links and enable in-field diagnosis. However, these TAPs create a shared attack surface: penetrating a single die can potentially expose control of the entire stack. Current countermeasures involve embedding a complete cryptographic engine in each chiplet, which increases the area and locks the protocol at tape-out, leaving it susceptible to future unknown attacks. This paper proposes a Software-Defined Secure Island (SDSI) architecture that decouples security policies from hardwired logic while satisfying non-functional requirements. Each chiplet instantiates an ultra-lightweight Secure Island Controller (SIC) macro that performs only two XORs and two additions per handshake. Meanwhile, a centralized secure island runs heavyweight cryptography in firmware using the multi-round SASL-JTAG+ protocol. SDSI enables scalable, adaptable test access protection by decoupling security from hardware. An FPGA implementation shows that the SIC macro occupies 11% of the area of an AES- 128 core and 37% of a SHA256 core, yet it supports 256 - to 512-bit keys with negligible growth. A security analysis demonstrates immunity to replay attacks because the authentication data is refreshed with each session. All future upgrades, such as longer keys, stronger hashes, and additional rounds, are delivered via firmware, providing scalable, field-upgradable protection for heterogeneous chiplet systems.

This paper proposes a novel Test Point Insertion (TPI) strategy to enhance the testability for multi-cycle Built-In Self-Test (BIST) for logic circuits. The approach leverages Multivariate Temporal-Spatial Graph Convolutional Neural Networks (MTS-GCN) and Reinforcement Learning to identify optimal Test Points (TPs). The proposed TPI method treats the testability information of a logic circuit as time-series data and employs Multivariate Time-Series Graph Neural Networks (MTGNN) to capture the relationship between the circuit's structural (spatial information) attributes and the temporal variability of signal line testability across capture cycles. A subsequent Multi-Layer Perceptron (MLP) computes the metric for each signal line to pinpoint potential TPs based on the extracted temporal-spatial features. Experimental evaluation based on benchmark circuits confirms the efficacy of the proposed model, which is trained with Deep Q-Networks (DQN), in improving the fault detection for multi-cycle logic BIST.

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST) . Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power-on Self-Test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST.

To attain the requirement of ISO26262 standard, the POST for automotive MCU needs to achieve high Latent Fault (LF) metric (>90% for ASIL D) within limited test application time (TAT). In this paper, we propose a new DFT technique named Fault-Detection-Strengthened (FDS) method to enhance the effect of test pattern reduction of the multi-cycle test for shortening the TAT of POST, and develop an original in-house tool named FVP-TPI (Fault Vanishing Point-TPI) to implement the FDS method to automotive MCU. The evaluation results on a latest commercial automotive MCU (62M gates) confirm the effectiveness (test volume compaction) and the practicability (smaller hardware overhead, shorter period of DFT) of the method.

Recently, reconfigurable devices are gaining increased attention for the development of IoT, Automotive and AI system. A new type of fine-grained reconfigurable device named MRLD (Memory Based Reconfigurable Logic Device) has been proposed which is constructed by general SRAMs without any programmable interconnect resources. It should be a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In this paper, we overview the architecture and the operation principle of MRLD. We also propose a test strategy and algorithms of pattern generation for the interconnect defects referred to stuck-at and bridge faults under MRLD. Experimental results confirmed the effectiveness of the proposed test method.

BIST based field testing is a promising way to guarantee the functional safety of intelligent and autonomous systems. To improve the fault coverage with less random patterns for BIST, sequentially observing some flip-flops (FFs) during multi-cycle test is useful. In this paper, we propose the methodology for selecting the Fault-Detection-Strengthened FFs in multi-cycle test by evaluating the structure of a circuit. The experimental results of ITC99 benchmarks and a real Electronic Control Unit (ECU) circuit show the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction.

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order to handle unknown states due to the non-reset table flip-flops, we introduce heuristic techniques. The effectiveness of the proposed methods are evaluated by the experimental results for benchmark circuits.

In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy. In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault. However, a flip-flop may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault. In the paper, we first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test. Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods.

With shrinking of LSIs, the diversification of defective mode becomes a critical issue. As a result, test patterns for stuck-at faults and transition faults are insufficient to detect such defects. N-detection tests have been known as an effective way for achieving high defect coverage, but the large number of test pattern counts is the problem. In this paper, we propose metrics based on the fault excitation functions and the propagation path function to evaluate test patterns for transition faults. We also propose the method for selecting the test patterns from the N-detection test set. From the experimental results, we show that the set of selected test patterns can detect the larger number of faults than other test set with the same number of test patterns.

Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods.

This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.

Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test for an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters. In this paper, we propose a new class of the pair of tests for the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.

This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.

Defects in the modern LSIs manufactured by the deep-submicron technologies are known to cause complex faulty phenomena. Testing by targeting only stuck-at or bridging faults is no longer sufficient. Yet, increasing defect coverage is even more important. A stuck-open fault model considers transistor level defects, many of which are not covered by a stuck-at fault model. Further, test vectors for stuck-open faults also have the ability to detect the defects modeled by delay faults. This paper presents test generation methods for stuck-open faults using stuck-at test vectors and stuck-at test generation tools. The resultant test vectors achieve high coverage of stuck open faults while maintaining the original stuck-at fault coverage, thus offering the benefit of potential better defect coverage. We consider two types of test application mechanisms, namely launch on capture test and enhanced scan test. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods

For deep-sub micron technology based LSIs, conventional stuck-at fault model is no longer sufficient for fault test and diagnosis. This paper presents a method of fault diagnosis for transistor shorts in combinational and full-scan circuits under logic test environment. Description of a short requires a very large number of physical parameters, and hence it is difficult, if not impossible, to describe precisely the behavior of transistor shorts. Therefore, two types of transistor short models were defined and algorithms to address the diagnostic problem were developed. The novelty of the algorithms is that they use conventional stuck-at fault simulation methodologies to diagnose transistor level shorts. Experiments were conducted on benchmark circuits to demonstrate the effectiveness of the method

In this paper, we propose techniques for finding Xs in test sequences for sequential circuits. Also we show two applications that utilize the obtained test sequences with Xs: reduction of the power during test and test compaction.

Recently, manufacturing defects including opens in the interconnect layers have been increasing. Therefore, a failure analysis for open faults has become important in manufacturing. Moreover, the failure analysis for open faults under BIST environment is demanded. Since the quality of the failure analysis is engaged by the resolution of locating the fault, we propose the method for locating single open fault at a stem, based on only detecting/un-detecting information on tests. Our method deduces candidate faulty stems based on the number of detections for single stuck-at fault at each fan-out branches, by performing single stuck-at fault simulation with both detecting and un-detecting tests. To improve the ability of locating the fault, the method reduces the candidate faulty stems based on the number of detections for multiple stuck-at faults at fanout branches of the candidate faulty stem, by performing multiple stuck-at fault simulation with detecting tests.

We have proposed a method for identifying candidate single stuck-at faults based on the ambiguous test set (Takahashi et al., 2003). In this paper, we propose enhancing methods for diagnosing single/multiple stuck-at faults under BIST environment to reduce the number of candidate faults. The enhancing method uses the number of detections for candidate faults and the first detecting test to diagnose the candidate faults. Moreover, we propose an enhancing method for diagnosing multiple stuck-at faults by using test-pairs.

We propose a method to find don't care (X) values in a test sequence for a sequential circuit. Given a fully specified test sequence generated by a sequential ATPG, the proposed method produces a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence.

For recent VLSIs designed for low power, reduction of power dissipation during test is one of the most important problems. This paper presents a method to reduce power dissipation during test for sequential circuits. The goal is to obtain test vectors for sequential circuits that achieve low power dissipation. In our method, test vectors generated by ATPG are given and they are improved to reduce power dissipation without losing the original stuck-at fault coverage. Due to the correlation between power dissipation and the number of transition gates, the number of transition gates is evaluated for each test vector during modification of test vectors. In order to keep the original fault coverage, logic simulation and fault simulation are performed, every time a test vector is modified. The effectiveness of our method is shown by experimental results for ISCAS '89 benchmark circuits.

In this paper, we propose a test generation method for double stuck-at faults. The proposed method consists of three main parts: (1) fault simulation with the application of test patterns generated for single stuck-at faults; (2) identification of undetectable faults; and (3) test generation using a test generator for single stuck-at faults. The effectiveness of the proposed method is shown by experimental results for ISCAS'85 benchmark circuits.

Describes two methods of diagnosing crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare with observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. In these methods, if the simulated values agree with the observed responses, then the simulated fault is added to a set of suspected faults, otherwise the simulated fault is removed from the set of suspected faults. The diagnosis methods repeat the above process for each time frame to identify the suspected faults. The first method is a basic method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The second method uses state information and focuses on reducing the CPU time for diagnosing the faults. The CPU time is reduced by using stored state information to calculate the primary output values at the present time frame. Experimental results for ISCAS'89 benchmark circuits show that the number of suspected faults obtained by our methods is sufficiently small, and the second method is substantially faster than the first method.

Abstract| This paper surveys recent research related to IDDQ testing, particularly focuses on fault models and test generation methods.(1) The paper pro videsa taxonomy of fault models that hav e been studied in literature, and classi es these models into a small set of faults.(2) The paper describes ecient test generation methods and fault simulation methods.T est compaction methods, including reduction of the total number of test v ectors and selection of IDDQ measurement v ectors, are also described.

Proposes a static test compaction method for sequential circuits with reset states under a single stuck-at fault assumption. The proposed method first finds unremovable vectors by fault-dropping fault simulation or by non-fault-dropping fault simulation. Next, a subset of test vectors other than unremovable vectors are replaced with a reset signal. Detection of faults detected by an original test sequence is guaranteed by logic simulation and fault simulation for test subsequences. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method.

This paper presents fault simulation techniques for selecting a small number of IDDQ measurement vectors from a given test sequence while maintaining the original fault coverage. The proposed method covers a class of bridging faults and uses parallel fault simulation wherever possible. Experimental results are presented to demonstrate the effectiveness of the proposed method.

One of the major unsolved and ignored but significant problems is the reduction of the long testing time for IDDQ testing of CMOS circuits. Since IDDQ must be observed after dynamic current disappears, testing time is much longer than logic testing. This paper presents a method to reduce the observation time for IDDQ testing. The proposed method is a static method which focuses on selection of vectors to be observed instead of removing vectors. Experimental results are presented to demonstrate the effectiveness of the proposed method.

This paper presents a design-for-testability technique aimed at test length reduction for scan designed circuits. A new concept, called partially parallel scan chain, is introduced. In the partially parallel scan chain, some flip-flops are arranged in parallel so that the number of scan shift clocks is reduced. Retiming techniques are used to select the flip-flops arranged in parallel. The flip-flops are repositioned only during test vector generation, but not actually. Then the test vectors generated for the retimed circuit are applied to the original circuit. In this paper, the difference in detectability of faults between the retimed circuit and the original circuit is also discussed. Finally experimental results are shown.

This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. In this work, retiming, which repositions flip-flops, is introduced to enhance the effect of the reduced scan shift. When the number of flip-flops is reduced by the retiming, the test length is also reduced. Furthermore, this paper shows that the test length can be reduced even when the number of flip-flops is not reduced by the retiming. Under applying the reduced scan shift, the change of the control requirement to flip-flops by the retiming causes the reduction of scan shifts. Test vectors for the retimed circuit can be obtained by modifying the test vectors for the original circuit. Then the computing time to newly generate test vectors can be saved. Finally experimental results are given to show the effectiveness of the proposed method.

This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences. In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible. For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors. Experimental results for ISCAS'89 benchmark circuits are given to show the effectiveness of this method.