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Madhu A. Metha

dblp:87/5644 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault diagnosis		 0.011977
Synthesis of Optimal Amiguity Resolver Functions · IEEE Trans. Computers 1977
Electronic design automation
hardware verification and test		 0.011977
Synthesis of Optimal Amiguity Resolver Functions · IEEE Trans. Computers 1977
Electronic design automation › hardware verification and test › design for testability
test point selection		 0.011977
Synthesis of Optimal Amiguity Resolver Functions · IEEE Trans. Computers 1977

Methods — techniques the papers use, named apart from their topics

optimal ambiguity resolver synthesis · 0.0
YearPublicationVenuePosition
1977 Synthesis of Optimal Amiguity Resolver Functions
abstract
Large-scale integration (LSI) circuits impose particular constraints and present special opportunities for improving the diagnostic resolution of a digital system. In particular, bond failures represent a very significant failure mode in integrated circuits, so it is important to be able to identify a fault on an input/output lead to a single bus of a least replaceable unit, and it is desirable to do this using a minimum number of test points.
Madhu A. Metha, William Bridges Smith
 IEEE Trans. Computers1