Demo Data from EDBT 2026 / reviewers in the wild / expert
Shigeo Noda
dblp:87/5911
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 91% Integrated circuit design · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › placement and routing
gate array layout |
0.0 | 1 | 1985 | Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985 |
Electronic design automation
physical design |
0.0 | 1 | 1985 | Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985 |
Electronic design automation › physical design
placement and routing |
0.0 | 1 | 1985 | Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985 |
Integrated circuit design › ASIC design
CMOS gate array |
0.0 | 1 | 1985 | Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985 |
Methods — techniques the papers use, named apart from their topics
automatic layout algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1985 | Automatic layout algorithms for function blocks of CMOS gate arraysabstractAutomatic layout algorithms, placement and routing, for function blocks of CMOS gate arrays are presented. Shigeo Noda, Hitoshi Yoshizawa, Etsuko Fukuda, Haruo Kato, Hiroshi Kawanishi, Takashi Fujii |
DAC | 1 |