Smartphones have become more ubiquitous than ever. People are installing various applications on their smart-phone to fit into their lifestyle. Existing research shows that there are patterns within the ways people access those applications, whether it involves particular locations, particular ranges of time, or many other factors. In this research, through a collaboration with a commercial company, we collected usage data from a popular smartphone application that gives its users access to digital flyers information for shops and supermarkets throughout Japan. Our early experiments found that the pattern information contained inside the data could be used to authenticate users. In this research, we are proposing a behavioral authentication model implementing customized learning classifier systems to search through vast amount of possible patterns to authenticate users of the application. Our early findings for this ongoing research demonstrate that our model can feasibly be a good alternative for additional authentication factor to implicitly authenticate users beyond the initial registration.

A visual homograph attack is a way that the attacker deceives the web users about which domain they are visiting by exploiting forged domains that look similar to the genuine domains. T. Thao et al. (IFIP SEC'19) proposed a homograph classification by applying conventional supervised learning algorithms on the features extracted from a single-character-based Structural Similarity Index (SSIM). This paper aims to improve the classification accuracy by combining their SSIM features with 199 features extracted from a N-gram model and applying advanced ensemble learning algorithms. The experimental result showed that our proposed method could enhance even 1.81% of accuracy and reduce 2.15% of false-positive rate. Furthermore, existing work applied machine learning on some features without being able to explain why applying it can improve the accuracy. Even though the accuracy could be improved, understanding the ground-truth is also crucial. Therefore, in this paper, we conducted an error empirical analysis and could obtain several findings behind our proposed approach.

The amount of data available has grown rapidly in recently years, not least in the context of Industrialization 4.0 and the advent of Cyber Physical Systems (CPS) and IoT devices. Thus, Machine Learning and Big Data analysis are being taken seriously as promising solutions to cope with the challenges of exponentially growing data. A widely known and widely used approach to quantify the relationship between a dependent variable and multiple numerical predictors is the Generalized Linear Model (GLM). In this paper, we introduce an approach to accelerate the GLM's fitting algorithm. Our approach is involved in two steps. First, reimplement GLM fitting algorithm which applies Normal Equation [1] method when solving the Linear Least Squares Equation. Then, we port the implemented GLM fitting to be executable with GPGPU. When Normal Equation method is applied to tall-skinny data, which is typically found in log data of CPS, solving the post Linear Least Squares equation becomes trivial, and the computational burden is transferred from solving that equation to matrix multiplication which can be parallelized in a straightforward manner. In an experiment employing actual user log access data, the Normal Equation method was executed 1.9 times faster when being executed in CPU, combined with 16.8-fold acceleration by GPGPU, leading to being 31.3 times faster overall.

A new circuit simulation system is presented with techniques "Subcircuit Balancing with Estimated Update operation count" (SBEU) and "Asynchronous Distributed Row-based interconnection parallelization" (A-DR). SBEU estimates Gaussian elimination cost of each subcircuit by counting number of update operations to achieve balanced circuit partitioning. A-DR makes it possible to overlap numerical operations and interprocessor communications in parallel Gaussian elimination of interconnection equations. On a 16-PE distributed memory parallel machine, an experimental simulation shows 9.9 times speedup over 1PE and distribution of the time consumed for each subcircuit is within /spl plusmn/26% deviation from the median.

The authors describe a novel parallel detailed router named PROTON (parallel router on a parallel machine) with various new features. These features include: a parallelized line search algorithm based on parallel breadth first search; extraction of a higher degree of parallelism by simultaneous routing of multiple nets using the result of the global router; a parallel router on a quasi-shared-memory based MIMD parallel machine; and a detailed router supporting multilayer channelless gate arrays with complex industrial design rules. PROTON is implemented on an MIMD parallel machine named Cenju, which consists of 64 microprocessors. In order to improve routing speed, PROTON incorporates two levels of parallelism, namely magnet parallelism and net level parallelism. A speedup of 43 times has been achieved using 64 processors for a medium-scale channelless gate array (1537*1790 grids, 12591 pin pairs).>

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-level software simulators in the case of 31 processors used. HAL III can be expanded to 127 processors. HAL III can also be used as a fault simulator. Its simulation speed can be estimated more than a hundred times faster than software simulators. HAL III has been successfully used in practical VLSI designs.>

The architecture of a proto-type functional level simulator element of a massively parallel machine (MAN-YO) designed for logic design automation is presented. At functional level, hardware systems are described in a hardware description language, FDL. The FDL description is compiled into stack oriented intermediate language instructions. Communicating with other gate level/block level/ functional level processors, each functional simulator interprets the compiled instructions and simulates various circuits using 4-value logic. In order to realize high speed processing of 4-value logic/arithmetic operations, the functional simulator utilizes low-level parallelism realized by 3 ALUs which are controlled by the different fields of a long horizontal type microinstruction. By utilizing low-level parallelism at processor level, as well as processor level parallelism, high speed execution of mixed level simulation becomes possible. The system also provides further performance enhancement by compiling often used FDL macros into microcode. This paper describes an outline of the MAN-YO (Japanese for ten thousand leaf-nodes in the processor tree), a brief description of FDL, and the architecture of the functional level simulator element (called FDLPE). A rough performance based on the current design is also described.

We proposed a computer with low-level parallelism as one of the basic computer architectures and built a large scale experimental system called QA-2. By low-level parallelism, we mean that a long-word instruction controls simultaneously many ALUs, busses, registers and memories in a mode of fine-grained parallelism. The QA-2 employs a 256-bit instruction by which four different ALU operations, four memory accesses to different/continuous locations and one powerful sequence control are all specified and performed in parallel. If many simultaneously executable operations are detected and embedded in one instruction at compile time, this type of computer can provide a high-degree of performance for a wide variety of applications. This paper describes the architectural benefits and limitations of low-level parallelism in performing 3-D color image generation and interpreting Prolog/Lisp programs. The hardware organization with four ALUs, which are actually implemented in the QA-2, is verified to be adequate. In fact, nearly three out of four ALUs can work in parallel. Any architecture with more than four ALUs can not achieve a significant degree of performance enhancement. This paper also shows the degree of performance improvement achieved by the techniques such as ALU chaining and highly-structured sequence control mechanisms. As compared with the IBM 370 architecture, the QA-2 can generate 3-D color images in 1/5 of dynamic instruction steps. The compiler version of Prolog machine on the QA-2 is as fast (45K LIPS) as the ICOT's PSI. From all results, we expect that the QA-2 is a high-performance computer which will be utilized in the future personal computing environment.

This paper describes the architecture of a dynamically microprogrammable computer with low-level parallelism, called QA-2, which is designed as a high-performance, local host computer for laboratory use. The architectural principle of the QA-2 is the marriage of high-speed, parallel processing capability offered by four powerful Arithmetic and Logic Units (ALUs) with architectural flexibility provided by large scale, dynamic user-microprogramming. By changing its writable control storage dynamically, the QA-2 can be tailored to a wide spectrum of research-oriented applications covering high-level language processing and real-time processing.