As global efforts to explore the Moon intensify, the need for high-quality 3D lunar maps becomes increasingly critical—particularly for long-distance missions such as NASA’s Endurance mission concept, in which a rover aims to traverse 2,000 km across the South Pole–Aitken basin. Kaguya TC (Terrain Camera) images, though globally available at 10 m/pixel, suffer from altitude inaccuracies caused by stereo matching errors and JPEG-based compression artifacts. This paper presents a method to improve the quality of 3D maps generated from Kaguya TC images, focusing on mitigating the effects of compression-induced noise in disparity maps. We analyze the compression behavior of Kaguya TC imagery, and identify systematic disparity noise patterns, especially in darker regions. In this paper, we propose an approach to enhance 3D map quality by reducing residual noise in disparity images derived from compressed images. Our experimental results show that the proposed approach effectively reduces elevation noise, enhancing the safety and reliability of terrain data for future lunar missions.

Synthetic, or artificial data is used in security applications such as protection of sensitive information, prediction of rare events, and training neural networks. Risk and trust are assessed specifically for a given kind of synthetic data and particular application. In this paper, we consider a more complicated scenario, - biometric-enabled cognitive cognitive biometric-enabled identity management, in which multiple kinds of synthetic data are used in addition to authentic data. For example, authentic biometric traits can be used to train the intelligent tools to identify humans, while synthetic, algorithmically generated data can be used to expand the training set or to model extreme situations. This paper is dedicated to understanding the potential impact of synthetic data on the cognitive checkpoint performance, and risk and trust prediction.

Terrain knowledge around unmanned ground vehicles (UGVs) is vital for autonomous navigation. Having global understanding of the surroundings of UGVs is important, although the field of view from UGVs is very limited. Thus, we utilize an aerial vehicle to provide a large terrain map from sequential aerial images. In this paper, we present multiple techniques to accelerate the process of terrain classification so that it can run onboard on the aerial platform. The main techniques used to accelerate the process is a "knowledge distillation" of a deep neural net to a shallower one, and a super pixel implementation. We evaluated our system on Jetson TX1 with actual images collected from a weather balloon which confirmed the effectiveness of the proposed system.

This paper introduces a tool designed to provide an innovative and insightful way of exploring Earth observation data content beyond visualization, by addressing a visual analytics process. The considered framework combines machine learning and visualization techniques, empowered through human interaction, to gain knowledge from the data. The proposed tool- eVADE leverages the methodologies developed in the fields of information retrieval, data mining and knowledge representation by the means of a visual analytics component. eVADE increases users capability to understand and extract meaningful semantic clusters together with quantitative measurements, presented in a suggestive visual way.

This paper introduces humanoid-oriented movement writing (HOM), focusing on a notation in which body postures allow easy visual interpretation by both humans and humanoid robots. HOM Writing, derived from Sutton Movement Writing and Shorthand [1], is a natural modality for encoding the movements that humans perform during various work activities. Beyond its use as a record of human movement, the intent is to use the writing as a modality of communicating to robots what movements to execute. Humanoid robots could directly map the key postures represented in the notation to their own postures, imitating the postures captured in the description, and calculating intermediate postures by interpolation. A motion generator would ensure the motor control needed to create continuous movements. This paper focuses on the generation of the activity movement scripts, and addresses two modalities of producing the scripts: 1) `hand-coded' by a human, using an editor, and 2) automatic extraction from video, e.g. from video-recordings of a human performing an activity. A software tool developed to allow easy script writing, the HOM Editor, is described and illustrated in hand-coding of a sequence of movements. The automatic generation of scripts from video is done using the pose estimation system by Yang and Ramanan [2], which takes an image and produces the joint coordinates of the limb parts; this is illustrated with a task of moving and arranging chairs. The posture extraction from a video provided by a single camera may often lead to occlusions of body parts during activities in which objects are manipulated. We show the advantages of using an additional camera, which significantly increases the correct posture estimation, and discuss how to further improve the automatic generation of scripts.

A recent NASA Innovative Advanced Concepts study suggests that several reflectors placed around the perimeter of Shackleton Crater may be capable of redirecting uninterrupted solar energy to a region within the crater year-round-effectively creating an energy oasis in the otherwise dark and cold extreme environment. This work further explores this concept by identifying sets of reflector placement locations around the perimeter of Shackleton Crater that maximize the amount of time in which at least one reflector in the set has access to sunlight. Using LRO LOLA data, a 3D model of Shackleton Crater and the surrounding terrain is created. Using a ray-tracing algorithm, synthetic imagery of this region is then generated using ephemeris data for the year 2020, from which an illumination model is generated. A placement optimization search algorithm is then developed, and results are shown for cases of 1, 2, and 3 reflectors over a search space focused on the western ridge of the crater. Results indicate that three reflectors strategically placed around the perimeter of the crater would be capable of providing energy to an area within the crater for at least 92.5% of the year if placed at surface level, or at least 96.8% if placed 100 meters above the surface.

The advantage of using collaborative brain-computer interfaces in improving human response in visual target recognition tests was investigated. We used a public EEG dataset created from recordings made using a 32-channel EEG system by Delorme et al. (2004) to compare the classification accuracy using one, two, and three EEG signal sets from different subjects. Fourteen participants performed a go/no-go categorization task on images that were presented very briefly, with the target images of natural photos of animals and distractor images of photos that did not contain animals. First, we compared the EEG responses evoked by the target and distractor images, and it was determined that the P300 (i.e., a positive deflection in voltage with a latency of 300 ms) response evoked by the target images was significantly higher than that evoked by the distractor images. Second, we calculated and compared the classification accuracy using one, two, and three EEG signal sets. We used a linear support vector machine with 5-fold cross validation. Compared to the results obtained from single brain prediction (79.4%), the overall accuracy of two- and three-brains prediction was higher (89.3% and 88.7%, respectively). Furthermore, the time required to achieve 90% accuracy was significantly less when using EEGs from two and three brains (100 ms) than when using one brain (230 ms). These results provide evidence to support the hypothesis that one can achieve higher levels of perceptual and cognitive performance by leveraging the power of multiple brains through collaborative brain-computer interfaces.

This paper addresses the human-centered control of a team (pack) of quadrotors. The control is remote, over the internet. Using simple telepresence tools (video in Skype, showing remote imagery from a ground camera, and from the quadrotors' own livestreaming cameras) the operator uses a command language, UAVL (standing for Unmanned Aerial Vehicle Language) to control quadrotors' behaviors. Seventeen hand gestures are used to express the commands; these are decoded by processing EMG signals collected with an array of EMG electrodes embedded in a BioSleeve mounted on the forearm. Extending prior work with an Unmanned Ground Vehicle Language (UGVL) used with ground robots, UAVL encodes commands used to control quadrotors, individually, or as a team, in direct teleoperated flight, or in preprogrammed flight patterns triggered by the commands.

We explored the possibility of controlling a spacecraft simulator using an analogue Brain-Computer Interface (BCI) for 2-D pointer control. This is a difficult task, for which no previous attempt has been reported in the literature. Our system relies on an active display which produces event-related potentials (ERPs) in the user's brain. These are analysed in real-time to produce control vectors for the user interface. In tests, users of the simulator were told to pass as close as possible to the Sun. Performance was very promising, on average users managing to satisfy the simulation success criterion in 67.5% of the runs. Furthermore, to study the potential of a collaborative approach to spacecraft navigation, we developed BCIs where the system is controlled via the integration of the ERPs of two users. Performance analysis indicates that collaborative BCIs produce trajectories that are statistically significantly superior to those obtained by single users.

We introduce a novel person identification method for a surveillance system of much wider area than conventional systems using CCTV cameras. In the proposed system, we install cameras to rooftops of buildings or a low altitude airship, and identify people by gait features extracted from shadows, which are projected on the ground by the sun in the daytime or lights in the evening. Since conventional systems extract gait features from actual body area, the correct classification ratio is reduced due to the lack of information of body area, in case that images are captured by overhead cameras. On the other hand, the proposed system enables to identify people by gait features which are extracted from shadows projected on the ground, even if images are captured by overhead cameras. In the proposed system, shadow areas projected on the ground are extracted automatically from captured images, and then analyze dynamics of shadow areas by the spherical harmonics. Experiments of person identification using actual outside images revealed that the proposed method showed the best performance than conventional methods, and the results indicate the feasibility of person identification based on shadow analysis.

People identification has numerous applications, ranging from surveillance/security to robotics. Face and body movement/ gait biometrics are the most important tools for this task. Traditional biometrics use direct observation of the body, yet in some situations a projection may offer more information than the direct signal, for example the shadow of a person observed from overhead, e.g. from an unmanned aerial vehicle, may contain more detail than the top view of the head/body. We introduced the idea of shadow biometrics, exploiting biometrics information in human shadow silhouettes as derived from video imagery; this enables “overhead biometrics”, for recognition of human identity and behavior from high altitude airborne platforms using overhead video sequences. In this paper, we provide a demonstration of person identification based on gait recognition from shadow analysis. We describe compensation steps to address shadow variation with conditions of observation (sun position, etc). We define measures of shape variation, such as horizontal stripes on the silhouette, their length change in time determines frequency components (here spherical harmonics) for each gait cycle, which are used for classification by a k-nearest neighbor classifier. A correct classification rate (CCR) of 95 % was obtained. A degradation of CCR from 95 % to 75 % was observed when reduced spatial and temporal resolution from 1cm to 2cm, and from 30fps to 15fps.

Hardware implementation of genetic algorithms (GAs) is gaining importance because of their proven effectiveness as optimization engines for real-time applications (e.g., evolvable hardware). Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid predefined system architecture, and lack of support for multiple fitness functions. In this paper, we report the design of an IP core that implements a general-purpose GA engine that addresses these problems. Specifically, the proposed GA IP core can be customized in terms of the population size, number of generations, crossover and mutation rates, random number generator seed, and the fitness function. It has been successfully synthesized and verified on a Xilinx Virtex II Pro Field programmable gate arrays device (xc2vp30-7ff896) with only 13% logic slice utilization, 1% block memory utilization for GA memory, and a clock speed of 50 MHz. The GA core has been used as a search engine for real-time adaptive healing but can be tailored to any given application by interfacing with the appropriate application-specific fitness evaluation module as well as the required storage memory and by programming the values of the desired GA parameters. The core is soft in nature i.e., a gate-level netlist is provided which can be readily integrated with the user's system. The performance of the GA core was tested using standard optimization test functions. In the hardware experiments, the proposed core either found the globally optimum solution or found a solution that was within 3.7% of the value of the globally optimal solution. The experimental test setup including the GA core achieved a speedup of around 5.16× over an analogous software implementation.

Hardware implementation of Genetic Algorithms (GA) is gaining importance as genetic algorithms can be effectively used as an optimization engine for real-time applications (for e.g., evolvable hardware). In this work, we report the design of an IP core that implements a general purpose GA engine which has been successfully synthesized and verified on a Xilinx Virtex II Pro FPGA Device (XC2VP30). The placed and routed IP core has an area utilization of only 16% and clock period of 2.2ns (∼450MHz). The GA core can be customized in terms of the population size, number of generations, cross-over and mutation rates, and the random number generator seed. The GA engine can be tailored to a given application by interfacing with the application specific fitness evaluation module as well as the required storage memory (to store the current and new populations). The core is soft in nature i.e., a gate-level netlist is provided which can be readily integrated with the user’s system.

Technology trends are such that single event effects (SEE) are likely to become even more of a concern for the future. Decreasing feature sizes, lower operating voltage, and higher speeds, all conspire to increase susceptibility to single event upsets (SEU). Upset in avionics is an established concern. Upset at the ground level is becoming a concern for manufacturers of microelectronics for terrestrial applications. The use of flip-chip packaging and multiple levels of metals further exacerbate the problem. Typical methods of mitigation that either increase the transistor count or reduce IC performance are not acceptable to commercial manufacturers. SOI technology may help in this regard, but is not a magic bullet to end all SEE concerns. We present unique schemes to model and rectify single event disruption in combinatorial and synchronous parts of a reconfigurable architecture. We compare our scheme with different schemes already introduced and results are reported to prove the efficacy of the proposed radiation hardened reconfigurable architecture.

Reconfigurable architectures are becoming increasingly popular with space related design engineers as they are inherently flexible to meet multiple requirements and offer significant performance and cost savings for critical applications. As the microelectronics industry has advanced, integrated circuit (IC) design and reconfigurable architectures (FPGAs, reconfigurable SoC and etc) have experienced dramatic increase in density and speed. These advancements have serious implications for the reconfigurable architectures when used in space environment where IC is subject to total ionization dose (TID) and single event effects as well. Due to transient nature of single event upsets (SEUs), these are most difficult to avoid in space-borne reconfigurable architectures. We present a unique SEU fault tolerance technique based upon double redundancy with comparison to overcome the overheads associated with the conventional schemes

This paper demonstrates a method for functionality recovery due to total ionizing dose (TID) effects. The experiments are performed using a JPL-developed reconfigurable device, a field programmable transistor array (FPTA). The key idea of the approach is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. This method, demonstrated previously for electron beam radiation, is applied here for circuit recovery under Cobalt 60 sourced gamma rays radiation. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach, and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Domain-specific heterogeneous reconfigurable arrays provide high performance over generic field programmable gate arrays (FPGAs) while maintaining the flexibility for that particular domain. This paper introduces an embedded domain-specific reconfigurable array that targets discrete wavelet transforms (DWT) and also presents different configurations of the array to prove its suitability for complex algorithms which are part of changing standards like JPEG and MPEG etc. The proposed array is flexible in order to accommodate various 5/3 and 9/7 discrete wavelet transforms which makes it quite suitable for multimedia applications. Experimental results demonstrate that the proposed architecture is over 31% more efficient in terms of power consumption over standard FPGAs.

This paper presents a vision of humanoid robots as human's key partners in future space exploration, in particular for construction, maintenance/repair and operation of lunar/planetary habitats, bases and settlements. It integrates this vision with the recent plans for human and robotic exploration, aligning a set of milestones for operational capability of humanoids with the schedule for the next decades and development spirals in the Project Constellation. These milestones relate to a set of incremental challenges, for the solving of which new humanoid technologies are needed. A system of systems integrative approach that would lead to readiness of cooperating humanoid crews is sketched. Robot fostering, training/education techniques, and improved cognitive/sensory/motor development techniques are considered essential elements for achieving intelligent humanoids. A pilot project in this direction is outlined.

Radiation hard technologies for electronics are the conventional approach for survivability in high radiation environments. This work presents a novel approach based on evolvable hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. The paper demonstrates the approach using a JPL-developed reconfigurable device, a field programmable transistor array (FPTA), which shows recovery from radiation damage when reconfigured under the control of evolutionary algorithms. Experiments with total radiation dose up to 350kRad show that while the functionality of a variety of circuits, including a rectifier and a digital to analog converter implemented on a FPTA-2 chip, is degraded/lost at levels before l00KRad, the correct functionality can be recovered through the proposed evolutionary approach. The evolutionary algorithm controls the state of about 1,500 switches that determine configurations on the FPTA-2 programmable device. Evolution is able to use the resources of the reconfigurable cells, even radiation damaged components, to synthesize a new solution.

Traditionally, FPGAs have been the bastard step-brother of ASICs. They have been forced to act like ASICs and fit themselves into the ASIC development model. This has meant ignoring their unique strengths: reprogrammability, late-binding and run-time reconfiguration. Today, however, FPGAs are becoming more acceptable for their own merits. The majority of new design starts are FPGA designs. As FPGAs rise from under the shadow of their aging brother, should they continue to try to wear his hand-me-downs? Or is it time to develop more suitable models that lets them shine? At the same time, the old ASIC model is not even serving ASICs well, and new models for developing ASICs are emerging. All of this may encourage us to rethink how we should be programming FPGA-based systems. Possibilities include:

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. However, current technology can only ensure very limited lifetime in extreme environments. This paper describes novel experiments that allow adaptive in-situ circuit redesign/reconfiguration during operation in extreme temperature and radiation environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip (FPTA-2), which recovers functionality for temperatures until 28/spl deg/C and with total radiation dose up to 250kRad.

Evolutionary algorithms (EA) offer good promise for automated design of analog circuits as well as for adaptation and automatic reconfiguration of programmable devices. In particular, EAs facilitate the design of analog circuits for very specific requirements, such as those related to the implementation of fuzzy operators, or even of complete fuzzy systems. The paper starts with a brief overview of the evolutionary process applied to circuit design and of a family of analog programmable devices that support on-chip evolution. As a case study, we describe the evolutionary design of a fuzzy controller, using re-configurable analog chips models and unstructured representation. We were able to achieve a circuit that approximates the control surface of a 2-input fuzzy controller, mapping thus a full fuzzy system in only seven transistors. The paper presents evidence that EA can provide very compact solutions for implementation of fuzzy systems, and that programmable analog devices are an efficient and rapid solution for rapid deployment of fuzzy systems.

The paper presents some experiments in automatic reconfiguration of field programmable devices using evolutionary algorithms. The experiments use a Field Programmable Transistor Array (FPTA), reconfigurable at transistor level. While parasitic effects of imperfect switches interconnecting transistors deteriorate performance of conventional designs when mapped to the FPTA, evolutionary algorithms are able to find a working design solution. The experiments are performed with a stand-alone board-level evolvable system (SABLES) in which the evolutionary algorithm is implemented with a DSP. SABLES can automatically configure the FPTA in tens to hundreds of seconds, time in which evaluates /spl sim/100,000 circuit candidate solutions. The paper overviews some examples of evolutionary synthesis of analog circuits on the FPTA.

Color edge detection has been normally based on the vector extension of classical (scalar) derivative operators. This extension has been done either by the independent processing of each color component and aggregation of the partial results or by the synthesis of a special color space, featuring a single highly relevant component. These approaches fail to embed any visual perception information. This paper proposes the use of a perceptually relevant dissimilarity measure, based on a fuzzy color model and on a spatial symmetry color spread index as the basis of a color edge detector.

Evolvable hardware (EHW) addresses on-chip adaptation and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-oriented characteristics. This paper proposes an evolution-oriented field programmable transistor array (FPTA), reconfigurable at transistor level. The FPTA allows evolutionary experiments with reconfiguration at various levels of granularity. Experiments in SPICE simulations and directly on a reconfigurable FPTA chip demonstrate how the evolutionary approach can be used to automatically synthesize a variety of analog and digital circuits.

The paper presents and compares two approaches to design fault-tolerant evolvable hardware: one based on the fitness definition and the other based on the population statistics. The fitness approach defines, in an explicit way, the faults that the component may encounter during its lifetime and evaluates the average behavior of the individuals. The population approach uses the implicit information of the population statistics accumulated by the genetic algorithm over many generations. The paper presents experiments done using both approaches on a fine-grained CMOS field programmable transistor array (FPTA) architecture for the synthesis of a fault-tolerant XNOR digital circuit. Experiments show that the evolutionary algorithm is able to find a fault-tolerant design for the XNOR function that can recover functionality when lost due to not a-priori known faults, by finding new circuit configurations that circumvent the faults. Our preliminary experiments show that the population approach designs a fault-tolerant circuit with better performance using less computation than the fitness based approach.

This paper describes the design of a reconfigurable chip programmable at the transistor level and oriented to the implementation of evolvable hardware (EHW) experiments. We tackle the main issues referring to the conception of an evolutionary oriented reconfigurable architecture (EORA): the cell topology; interconnection between cells; transistor sizing; resistor and capacitor implementation in silicon; selection of input and output points; and reconfiguration aspects. A set of evolutionary experiments is described, serving as support for the design choices. Additionally, we propose novel approaches to overcome area requirements for the VLSI design, such as the use of differentiated configurable blocks and a variable interconnection density throughout the chip.

The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithms) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements and in the environment or faults, through its ability to reconfigure the hardware structure dynamically and autonomously. This capacity for adaptation is achieved via the use of GA search techniques, in our experiments, a fine-grained CMOS (complementary metal-oxide silicon) FPTA (field-programmable FPGA transistor array) architecture is used to synthesize electronic circuits. The FPTA is a reconfigurable architecture, programmable at the transistor level and specifically designed for EHW applications. The paper demonstrates the power of EA to design analog and digital fault-tolerant circuits. It compares two methods to achieve fault-tolerant design, one based on fitness definition and the other based on population. The fitness approach defines, explicitly, the faults that the component can encounter during its life, and evaluates the average behavior of the individuals. The population approach, on the other hand, uses the implicit information of the population statistics accumulated by the GA over many generations. The paper presents experiment results obtained using both approaches for the synthesis of a fault-tolerant digital circuit (XNOR) and a fault-tolerant analog circuit (multiplier).

The paper addresses the use of evolutionary algorithms in the design of electronic devices and circuits. In particular, the paper introduces the idea of evolutionary design of nanodevices, and illustrates it with the design of a resonant tunneling diode. A second experiment, this time using CMOS microdevices, illustrates the use of evolutionary algorithms for circuit design. The experiments were facilitated by an evolutionary design tool developed around a parallel implementation of genetic algorithms (using PGAPack), and device/circuit simulators (NEMO and SPICE). It is speculated that in the future, devices and circuits may be simultaneously co-designed.