Reconfigurable Intelligent Surfaces (RISs) are emerging as a key technology for enhancing wireless communications in smart city environments, offering robust, low-latency connectivity. This paper presents the design of an adaptive control system based on high-voltage, mixed-signal integrated circuits for controlling tunable RISs, tailored for wireless cellular communications in urban areas. The proposed system enables enhanced programmability by dynamically steering beams and fine-tuning signal reflections through the precise control of varactor diodes embedded within the RIS unit cells. This flexible system architecture supports real-time software reconfiguration, allowing RIS units to adapt to varying network conditions and scale seamlessly across smart city infrastructures. Simulated results on a 0.35 μm CMOS high voltage process technology demonstrate the circuit's ability to achieve low power consumption and high reconfiguration speed across a wide temperature range. The control electronics are separated from the RIS panels, this way enabling tiling of multiple surfaces for scalable, cost-effective deployment. This approach offers a promising pathway to meeting the growing demand for seamless, high-speed, and energy-efficient connectivity in next-generation smart city applications, including vehicular networks, Internet of Things, smart traffic management and smart infrastructure.

Reconfigurable intelligent surfaces (RISs) are recognized as a fundamental enabler for improving energy efficiency in 6G and future networks. However, the power consumption and the reconfiguration delay still need improvement for what is required at GHz frequencies, thus delaying their commercial adaptation. On that regard, this study proposes the incorporation of Integrated Circuits (ICs) with MOS varactor loadings as part of the RIS framework, to improve power consumption and speed, while having precise tuning of the reflection phase for individual unit-cells. The presented circuit design features an asynchronous digital circuit responsible for transmitting binary streams to digital-to-analogue converters, which in turn, bias MOS varactors that are directly connected to each unit-cell within the RIS. The use of asynchronous digital control circuits facilitates the development of ultra-low power, high-speed ICs, thereby enhancing the dynamic scalability of the RIS system. Simulated results of the asynchronous circuit are presented on a mature, cost-effective, CMOS 0.18 μm process technology, showing static power consumption of 40,63 μW, dynamic energy consumption of 474.43 pJ and reconfiguration delay of 23.38 ns. The simulations are accompanied by a scalability analysis and a discussion of potential capabilities, offering valuable insights for the future of ICs on RIS systems. The proposed approach and circuit provide flexibility and performance to RIS systems not achievable with conventional control systems due to their benefits of using clockless networking communication.

Metasurfaces, the two-dimensional counterpart of metamaterials, have caught great attention thanks to their powerful control over electromagnetic waves. Recent times have seen the emergence of a variety of metasurfaces exhibiting not only countless functionalities, but also a reconfigurable or even programmable response. Reconfigurability, however, entails the integration of tuning and control circuits within the metasurface structure and, as this new paradigm moves forward, new reliability challenges may arise. This paper examines, for the first time, the reliability problem in programmable metamaterials by proposing an error model and a general methodology for error analysis. To derive the error model, the causes and potential impact of faults are identified and discussed qualitatively. The methodology is presented and instantiated for beam steering, which constitutes a relevant example for programmable metasurfaces. Results show that performance degradation depends on the type of error and its spatial distribution and that, in beam steering, error rates over 10% can still be considered acceptable.

Chua's mem-components are ideal for creating adaptive metasurfaces for manipulating EM waves given that they hold their state without external biases. In this paper, we propose a generic adaptive reactive element that is in fact a memcapacitor/meminductor. This element makes use of a polymer that demonstrates reversible trans-cis photochemical isomerization, thus making it possible to change the distance between two conductive plates by up to 25%. Furthermore, a design methodology for utilizing these devices is presented.

A tunable metasurface absorber is presented in this work using an optically-programmable capacitor as the tuning element. The tuning element does not employ conventional semiconductor technologies to operate but rather a bases its tuning by changing the optomechanical properties of its dielectric, poly disperse red 1 acrylate (PDR1A). Doing so there are no conventional semiconductor devices in the RF signal path. The metasurface operates at a design frequency of 5.5 GHz and it achieves an optically-tuned bandwidth of 150 MHz, from 5.50 GHz to 5.65 GHz.

Metamaterials and metasurfaces have given possibilities for manipulating electromagnetic (EM) waves that in the past would have seemed impossible. The majority of metasurface designs are suitable for a particular frequency and angle of incidence. One long-sought objective is the design of programmable metasurfaces to dynamically manipulate a variety of incoming EM frequencies and angles. In order to do this, a large-scale mesh of networked chips are required below the metasurface, which apart from adapting electrical impedance properties, also communicate with each other, thus relaying information about meta-atom settings, as well as forwarding possible distributed measurements taken. This paper describes why an asynchronous mixed-signal ASIC is advantageous for the control of scalable, EM absorbing, metasurfaces.

This paper describes the design and development of a unique, body-worn vitals monitor that is able to acquire ECG, blood oxygen, body temperature and up to eight custom designed electronic stethoscopes for highly synchronized heart and lung sound auscultation. The proposed platform is a key component required for developing a Field Accident and Emergency Center Intelligent Monitoring System to acquire vital patient information and optimize medical resource allocation in overwhelming environments. The proposed platform also has enabled the collection of a novel highly synchronized data-set that is useful for research purposes in the field of emergency vital sign analysis. The design is unique in that it is the only known wearable platform that, in addition to a multitude of standard vital signals, also wirelessly transmits eight multichannel auscultatory streams to central nodes, i.e. to a local ambulance or to the nearest hospital.

A low-power, wide temperature range, radiation tolerant CMOS voltage reference is presented. The proposed reference circuit exhibits a voltage deviation of 0.8mV for 3-MeV protons total ionization dose of 2Mrad and a voltage deviation of 3.8mV for 10-keV X-rays total ionization dose of 4Mrad while being biased at the nominal supply voltage of 0.75V during X-ray irradiation. In addition, the circuit consumes only 4μW and exhibits a measured Temperature Drift of 15ppm/°C for a temperature range of 190°C (−60°C to 130°C) at the supply voltage of 0.75V. It utilizes only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any diodes or external components such as compensating capacitors. The circuit is radiation hardened by design (RHBD), it was fabricated using TowerJazz Semiconductor's 0.18μm standard CMOS technology and occupies a silicon area of 0.039mm2. The proposed voltage reference is suitable for high-precision and low-power space applications.

Efficient microcancer detection in the small intestine can be realised by infrared fluorescence endoscopy (IRFE), in conjunction with an infrared fluorescent-labeling contrast agent that is designed to be selectively uptaken by cancerous cells. In this paper we present a second generation screening capsule, which is able to measure IR fluorescence levels emitted by the fluorophore indocyanine green (ICG), at different concentrations. The presented mixed-signal system is contained within a compact ingestible capsule, which is however large enough to come into close contact with the intestine walls during peristalsis. In-vitro experiments have shown that the system is able to detect and discriminate low concentrations of ICG, in the nanomolar region, which is required to detect early cancer in the small intestine.

An all-subthreshold CMOS Voltage Reference architecture is presented, which achieves 3rdorder curvature compensation over a wide temperature range. The simulated performance of the proposed architecture with a supply voltage of 0.75V is 2 ppm/°C, over a temperature range of 190 °C (-45 °C to 145 °C). The high order curvature compensation is performed using the non-linearities of an NMOS device, operated in subthreshold, combined with the non-linearities of low-temperature-coefficient poly resistors and high-resistivity poly resistors. The topology achieves a power consumption of 2μW. The design does not require any external components.

The ability to recognize the behavior of individuals is of great interest in the general field of safety (e.g. building security, crowd control, transport analysis, independent living for the elderly). Here we report a new real-time acoustic system for human action and behavior recognition that integrates passive audio and active micro-Doppler sonar signatures over multiple time scales. The system architecture is based on a six-layer convolutional neural network, trained and evaluated using a dataset of 10 subjects performing seven different behaviors. Probabilistic combination of system output through time for each modality separately yields 94% (passive audio) and 91% (micro-Doppler sonar) correct behavior classification; probabilistic multimodal integration increases classification performance to 98%. This study supports the efficacy of micro-Doppler sonar systems in characterizing human actions, which can then be efficiently classified using ConvNets. It also demonstrates that the integration of multiple sources of acoustic information can significantly improve the system's performance.

The study of electrical brain activity (EEG) during anesthesia has received much attention over recent years. This can be attributed to the fact that such study has vast clinical and research implications. In this work we study how the linear temporal dynamics of EEG activity are affected by the administration of anesthetic agents. The measure of lagged auto-correlation (LAC) is applied to the EEG activity of 10 patients undergoing routine surgery and the evolution of the LAC features is tracked during transitions between wakefulness/unconsciousness. We report a reversible and widespread increase in LAC during anesthesia, with decreased variability compared to wakefulness. This corresponds to a less complex EEG activity during anesthesia as a result of anesthetic administration and suggests the future utilization of LAC as a feature for discriminating between wakefulness and anesthesia.

With the recent discovery of the memristor, and following the initial realization based on titanium dioxide (TiO2), a plethora of potential device implementations have emerged. In this paper we present a novel memristive device based on a nickel titanium (NiTi) smart alloy. The proposed memristors are very practical in that it is possible to add a smart metal layer on an existing semiconductor process with very few extra masks. By patterning different widths and lengths of these memristors, the designer can affect the properties of the memristor. Unlike memristors designed for memory storage applications, these devices can return to their original state over shorter time scales, thus lending themselves to dynamic neural processes, which are key components required for future biomimetic computer architectures.

We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

Spike Timing Dependant Plasticity (STDP) is a biologically-based Hebbian reinforcement learning rule for the unsupervised training of synaptic weights in spiking neural networks. We present a low complexity synthetic implementation of STDP using basic combinational digital logic gates. This approach attains comparable results to more complex implementations while utilizing only a fraction of the area. We use our STDP approach to replicate the experimental results of a balanced excitation experiment.

We present a quantitative analysis of the limits of the time-multiplexed Address Event Representation (AER) bus for on-chip connectivity of silicon neuron arrays. In particular, we evaluate its potential to support high density and low power neural arrays operating in the subthreshold regime. Our analysis shows that due to low clock frequencies when operating in the subthreshold regime, the traditional single AER bus does not scale to large neural arrays. We find that a switched mesh network improves scalability, however, a crosspoint architecture overcomes the bandwidth limitations altogether. By trading off area for improved performance, it increases the number of neurons that can be supported in a single chip neural array.

We present a micropower QCIF image sensor fabricated in 0.18μm CMOS technology. Low-power operation is achieved through a system-on-chip design methodology optimizing from device to architecture, yielding a 3-pin autonomous system. Supply voltage and reference are scaled down to 1.0V and 400mV, respectively. Compared to previous work, this imager consumes 42% less energy per pixel.

Memristors are passive circuit elements that behave as resistors with memory. The recently illustrated experimental realization of memristive behaviour of Polysilicon Nanowires has triggered interest in this concept, which is promising to a wide variety of application areas that include neuromorphic circuits. In order to progress with practical implementations that use this technology we need to expand our understanding of the conduction mechanisms in these structures and of the underlying relationship between device behavior and process manufacturing parameters. In this paper we explore these mechanisms through detailed simulation, which includes model calibration and correlation with experimental results. Through fitting of the test results we identify a unique set of density of states that characterize the particular technology implemented.

This paper proposes a new CMOS bandgap reference generator topology that allows a straightforward implementation of an exact curvature compensation method by using only poly-silicon resistors. This is achieved by using a second Opamp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. A superior theoretical performance than previously proposed architectures is achieved with respect to temperature sensitivity of the reference voltage. In nominal simulations, that was less than 0.lppm over a temperature range of -40 to 125 for a CMOS 0.35 μm technology. In practice, the proposed BGR is sensitive to device mismatch and thus resistor trimming is necessary if high performance is required.

This paper describes an ASIC developed as part of a neural prosthesis to restore balance to individuals with a dysfunctional vestibular end-organ. The device interfaces with inertia sensors; sensing acceleration in five degrees of freedom (three radial and two linear axis), and then conditions, processes and converts the signals to provide the artificial stimulus to the vestibulocochlear nerve. The IC described herein has been realised as part of a board-level solution, also including the sensors, power source and DC blocking capacitors. It is envisaged that this can be later implemented in a system-in-package (SiP) form to provide a totally implantable solution. We describe the design and implementation of the integrated circuit in a standard 0.35 mum CMOS technology.

This paper presents a novel hybrid CMOS/MEMS tilt sensor with a 5deg resolution over a 330deg range. The device uses a MEMS-based semicircular mass suspended from a rigid body, projecting a shadow onto the CMOS-based optical sensor surface. A one-dimensional photodiode array arranged as a uniformly segmented ring is then used to determine the tilt angle by detecting the position of the semicircular mass. The complete sensor occupies an area of under 2.5 m times 2.5 mm.

This papers presents a front-end circuit for interfacing to differential capacitive sensors, including certain micro- electromechanical systems (MEMS). The system combines a self- resetting, biphasic integrator with a difference timer, producing a word parallel output representing the differential capacitance. The measurable capacitance range is tunable by means of an input current bias and system clock frequency. For an input bias of lOnA and system clock of 128 KHz, the measurable capacitance range is +/-5 pF (to 8 bit resolution) consuming below 26 muW total system power.

This paper describes a novel partial-current-steering stimulation drive for implantable neural prosthetics. The drive hardware momentarily delivers a charge-balanced asymmetric stimulus to a dummy load before steering towards the stimulation electrodes. In this fashion, power is conserved whilst still gaining from the benefits of current steering. The circuit has been designed to be digitally programmable as part of an implantable vestibular prosthesis. The hardware has been implemented in AMS 0.35 mum 2P4M CMOS technology.

This demonstrator presents an ultra low power mixed-signal implementation of a cochlear prosthesis system. A laptop PC provides an audio stimulus to the cochlear chip. A microcontroller on the demonstrator board monitors the output channels of the chip and returns these to the PC to be displayed as a spectrogram. The audiological settings of the implant chip are controlled via a GUI running on the PC.

This paper presents a low-voltage, reduced-area CMOS bandgap reference (BGR) circuit for low-power applications. Significant area reduction is achieved by utilizing a resistive T-network in combination with layout-efficient opamp compensation. A complete analysis, including the dual-loop stability, reveals several tradeoffs between area, loop-gain, stability and offset sensitivity. Based on this analysis, a high-performance design, in a 0.18μmCMOS process, is presented.

We present a system level architecture for a scalable, mixed-signal, asynchronous processor, aimed at cortical computations. The design has been implemented in MIT Lincoln Lab's three-tier SOI-CMOS 0.18mum digital process. The main circuits are distributed in the two tiers; an asynchronous address-event based read/write middle tier and an odd symmetric spatial filter (8 orientations) on the bottom tier. The top tier includes a photosensitive pixel array (64times64) to facilitate testing and characterization of the system. A highspeed 2-phase asynchronous chip-to-chip communication protocol is built-in to facilitate system scalability