The increasing deployment of neural networks in safety-critical domains, such as autonomous driving and embodied artificial intelligence, has underscored the urgent need for fault-tolerant neural architectures. Hardware-induced faults stemming from soft errors, aging, or other disturbances can severely impair model performance. In this paper, we propose a hierarchical optimization framework that systematically designs fault-tolerant neural architectures from operator design to architecture search method, while minimizing both accuracy loss and computational cost. Specifically, we design a fully decoupled Winograd convolution operator (FD-WGC) that localizes the impact of bit-flip faults and reduces computational cost. We then expand the architecture search space by introducing fault-tolerant cells composed of the FD-WGC and complementary operators, enabling more flexible network construction. Within this expanded search space, we employ MOBO-NAS, a multi-objective Bayesian optimization based neural architecture search method, to efficiently explore neural architectures that balance accuracy, computational cost, and fault tolerance. Experimental results show that our framework enhances fault tolerance by up to 510× compared to state-of-the-art (SOTA) manually designed and automatically searched architectures, while maintaining comparable accuracy and reducing computational cost by up to 80%. Extensive evaluations across diverse hardware fault models further validate the generalizability and effectiveness of our proposed framework. All codes are available at https://github.com/cc-innocence/MOBO-NAS/tree/master.

In fields where fault tolerance is critical, such as aerospace and autonomous driving, the Triple Modular Redundancy (TMR) is widely utilized due to its high reliability, yet it comes with significant overhead. To mitigate this issue, Approximate TMR (ATMR) has emerged as a promising solution. However, few studies have addressed the multi-objective optimization problem between hardware saving and fault tolerance caused by approximation. This paper presents two pioneering multi-objective optimization frameworks tailored for fault-tolerant circuit design that leverage approximate redundancy to achieve this delicate balance. The first framework, Dynamic Adjustment Multi-Objective Optimization (DA-MOO), proposes a Dynamic Adjustment Optimized NSGA-II (DAON) algorithm utilizing parity expansion and dynamic probability adjustment to generate ATMR solutions. This method surpasses traditional TMR by halving area and power overhead while still achieving over 70% of fault coverage. Considering the computational intensity of DA-MOO, we further propose the Pre-Encoding Multi-Objective Bayesian Optimization (PE-MOBO) framework, achieving a 198x improvement in computational time over traditional methods. In summary, DA-MOO is well-suited for scenarios requiring a premium on reliability alongside cost-efficiency, such as in the commercial aerospace industry, while PE-MOBO is particularly advantageous for applications demanding rapid design cycles, like consumer electronics.

The growing demand for energy-efficient computing in resource-constrained devices necessitates approximate arithmetic solutions that balance accuracy and hardware cost. This article presents a family of logarithmic truncation-based approximate multipliers (LTAMs) for floating-point (FP) operations, including two hardware cost-optimized architectures (LTAM1and LTAM2) and an accuracy-focused lookup table (LUT)-based design (LTAM-LUT). All designs effectively address the systematic negative bias inherent in classical logarithmic multipliers through advanced error compensation methods. Based on a comprehensive analysis, a 6-bit mantissa truncation is identified as the optimal configuration. Under the 6-bit configuration, LTAM1-6achieves 52.9% area and 77.6% power-delay product (PDP) reduction compared to conventional logarithmic approximate multipliers, while LTAM2-6 provides 45.1% area and 70.4% PDP reduction. LTAM-LUT achieves 56.4% accuracy improvement over conventional logarithmic approximate multipliers with a mean relative error distance (MRED) of 1.68%, the lowest among all compared designs. These hardware efficiency gains are also validated across diverse application domains. In HDR tone mapping, LTAM-LUT achieves up to 7.0dB higher peak signal-to-noise ratio (PSNR) than conventional designs, while LTAM1-6and LTAM2-6 provide 1.1- and 4.6-dB improvements, respectively. For single-image super-resolution (SISR) on DIV2K ($\times 4$scale), LTAM-LUT preserves reconstruction quality nearly identical to exact arithmetic on HAT (29.73dB) and achieves up to 2.3dB higher PSNR than conventional logarithmic multipliers on EDSR, while LTAM1-6and LTAM2-6 consistently outperform prior approximate designs across all tested architectures, demonstrating superior accuracy–efficiency tradeoffs for error-tolerant applications.

As integrated circuits (ICs) continue to scale, soft errors pose a growing threat to system reliability—particularly in safety-critical applications. Among various circuit components, flip-flops (FFs) are especially susceptible to soft errors due to their state-holding nature, making them prime targets for selective hardening. However, such hardening introduces area and power overheads, necessitating careful tradeoffs. Existing methods typically rely on multiobjective optimization (MOO) algorithms to identify Pareto-optimal hardening strategies, yet their inherent randomness limits controllability, and they must be rerun entirely for each new circuit instance, resulting in poor adaptability. In this work, we propose a deep reinforcement learning (DRL)-based hardening optimizer that supports zero-shot generalization to unseen circuits. Built upon the advantage actor–critic (A2C) framework, our model is trained on synthetic circuits and learns to make sequential hardening decisions under strict resource constraints. A recurrent neural network (RNN) captures the historical context of prior hardening steps, while an attention mechanism dynamically focuses on FFs with high soft-error vulnerability at each decision step. Experimental evaluations on benchmark circuits demonstrate that our proposed framework achieves an average hypervolume (HV) improvement of 19.58%. Furthermore, the framework provides at least a$9.9\times $runtime speedup for individual circuits, offering an agile and generalizable solution for reliability-centric circuit design. The source code is available athttps://github.com/Magic00JuJu/ZACHO/tree/main

Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft error issue in digital circuits. However, a multi-objective optimization (MOO) problem obviously appears when utilizing the hardened counterparts to replace the original unreliable cells. This paper proposes a MOO framework based on Bayesian Optimization (BO) for balancing design metrics like area, Longest Path Delay (LPD)/power, and Soft Error Rate (SER) while hardening digital circuits, including combinational and sequential circuits. This framework comprises two phases: 1) data preprocessing and 2) multi-objective Bayesian optimization. The first phase makes this framework much more applicable for large-scale circuits through data dimensionality reduction. The second phase is characterized by utilizing a black-box approach to greatly promote the efficiency and accuracy of MOO. Experimental results on benchmark circuits demonstrate that the framework achieves a 1.34x improvement in accuracy, an 11.47x enhancement in efficiency, and a 0.77x reduction in SER, while exhibiting a 4.27x and 0.72x increase in area for combinational and sequential benchmark circuits, respectively, along with a 0.54x increase in LPD and a 1.25x increase in power for Triple Modular Redundancy (TMR) techniques.

With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 °C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications.

Single Event Upset (SEU) is one of the most susceptible reliability issues for CMOS circuits in a harsh environment, such as space or even a sea-level environment. Especially in the advanced nanoscale node, the phenomenon of Multi-node-upset (MNU) becomes more prominent. Although a lot of work has been proposed to solve this problem, most of them ignored the need for low power consumption. Particularly, most existing solutions are not effective anymore when operating in low supply voltage. Therefore, this paper proposes a novel Flip-Flop called TRIGON based on a single-phase-clocking structure to achieve low power consumption while being able to tolerate Double-node-upset (DNU), even when operating at lower supply voltages. The experimental results show that TRIGON has a significant reduction in the area and Power-delay-area-product (PDAP). Particularly, it achieves about 80% energy saving on average when the input is static compared with the state-of-the-art circuits.

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.