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Giancarlo Ripamonti

dblp:87/7495 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2009
0000-0002-9406-021XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Electronic design automation · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › packaging
package design		 0.112009
Signal Integrity Flow for System-in-Package and Package-on-Package Devices · Proc. IEEE 2009
Electronic design automation
signal integrity		 0.112009
Signal Integrity Flow for System-in-Package and Package-on-Package Devices · Proc. IEEE 2009
Integrated circuit design › packaging
system-in-package		 0.012009
Signal Integrity Flow for System-in-Package and Package-on-Package Devices · Proc. IEEE 2009
YearPublicationVenuePosition
2009 Signal Integrity Flow for System-in-Package and Package-on-Package Devices
abstract
As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.
Paolo Pulici, Gian Pietro Vanalli, Michele A. Dellutri, Domenico Guarnaccia, Filippo Lo Iacono, Giovanni Campardo, Giancarlo Ripamonti
 Proc. IEEE7