EDBT 2026 Demo / reviewers in the wild / expert
Bingcai Sui
dblp:87/7583
· DBLP profile ↗
6ranked-venue papers
1as first author
5since 2021 · last 2026
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 1 first-author · 4 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Uni-STC: Unified Sparse Tensor CoreabstractModern processors are increasingly adopting tensor cores as key computational units. Compared to existing designs for dense and structured sparsity, recent dual-side sparse tensor cores have evolved to support general sparsity. However, existing methods still face limitations on generality (incomplete sparse kernel support prevents broad applicability) and performance (outer-product/row-row schemes yield unsatisfactory hardware utilisation, data reuse, and energy efficiency). In this paper, we propose Uni-STC, a unified sparse tensor core that delivers high-performance dataflows for four key sparse kernels: sparse matrix-vector multiplication (SpMV), sparse matrixsparse vector multiplication (SpMSpV), sparse matrix-multiple vector multiplication (SpMM), and sparse general matrix-matrix multiplication (SpGEMM). To efficiently support these diverse sparse workloads, we first introduce BBC, a unified sparse format co-designed with Uni-STC's dataflow. We then design UniSTC's architecture supporting (1) fine-grained task partitioning to improve resource utilisation, (2) parallel sparse-tile processing to enhance data reuse, and (3) a dynamic network to reduce intermediate data movement and energy consumption. Evaluated across 2893 SuiteSparse and 302 DLMC matrices, Uni-STC demonstrates significant improvements, outperforming the state-of-the-art RM-STC with a$2.21 \times$geomean speedup and$2.96 \times$higher energy efficiency. Haocheng Lian, Meichen Dong, Yijie Nie, Junzhong Shen, Chun Huang 0006, Bingcai Sui, Weifeng Liu 0002 |
HPCA | 10 |
| 2026 | Revisiting Global Value Prediction: A Resurgent Complement to Local Predictors
Ling Yang 0008, Libo Huang 0002, Bingcai Sui, Sheng Ma, Yongwen Wang, Li Shen 0007, Qianming Yang, Songwen Pei |
ISCA | 4 |
| 2024 | MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core ProcessorabstractGeneral-purpose processor vendors have integrated customized accelerator in their products due to the widespread use of General Matrix-Matrix Multiplication (GEMM) kernels. However, it remains a challenge to further improve the flexibility and scalability of these GEMM-enhanced processors to cater to the emerging large-scale GEMM workloads. In this paper we propose MACO, a novel loosely-coupled multi-core general-purpose archi-tecture optimized for GEMM-related applications. To enhance the programmability and flexibility of MACO, the paper introduces a tile-based instruction set architecture. Additionally, the paper presents techniques such as hardware-assisted data prefetching and locking, and predictive address translation to further enhance the computational efficiency of MACO for GEMM workloads. The experimental results demonstrate that MACO exhibits good scalability, achieving an average computational efficiency of 90 % across multiple cores. Furthermore, evaluations on state-of-the-art deep neural networks show that MACO can achieve up to 1.1 TFLOPS with 88 % computational efficiency, indicating its adaptivity to deep learning workloads. Bingcai Sui, Junzhong Shen, Caixia Sun |
DATE | 1 |
| 2024 | ImSPU: Implicit Sharing of Computation Resources Between Vector and Scalar Processing Units
Hongbing Tan, Guichu Sun, Liquan Xiao, Yuanhu Cheng, Quan Deng 0003, Bingcai Sui, Yongwen Wang, Libo Huang 0002 |
Euro-Par (2) | 9 |
| 2022 | RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core
Yuanhu Cheng, Libo Huang 0002, Yi-Jun Cui, Sheng Ma, Yongwen Wang, Bingcai Sui |
J. Comput. Sci. Technol. | 6 |
| 2009 | Comments on "Leading-One Prediction with Concurrent Position Correction"abstractIn this report, we first point out and analyse an error in the implementation of the pre-encoding logic in the LOP module proposed in [1], and then present a modification method. Rong Ji, Zhiqiang Ling, Xianjun Zeng, Bingcai Sui, Yingjie Feng |
IEEE Trans. Computers | 4 |