Incomplete data in smart grid measurement tools (SGMT) poses significant challenges for accurate monitoring and decision making. Traditional autoencoders with fixed loss functions struggle to handle heterogeneous corruption patterns—dense, low-amplitude noise and sparse, high-impact anomalies. This paper presents a multi-metric adaptive autoencoder designed for recovering incomplete SGMT data (MMAS). By combining diverse Lp-norm autoencoders with an adaptive weighting mechanism and nonnegative, density-aware optimization, MMAS effectively captures both noise and anomaly patterns. Experimental results on real-world data show that MMAS consistently outperforms baseline methods in both recovery accuracy and downstream tasks. The proposed framework offers a robust and practical solution for SGMT data recovery under varying sparsity conditions.

In the past decade, automatic product description generation for e-commerce have witnessed significant advancement. As the services provided by e-commerce platforms become diverse, it is necessary to dynamically adapt the patterns of descriptions generated. The selling point of products is an important type of product description for which the length should be as short as possible while still conveying key information. In addition, this kind of product description should be eye-catching to the readers. Currently, product selling points are normally written by human experts. Thus, the creation and maintenance of these contents incur high costs. These costs can be significantly reduced if product selling points can be automatically generated by machines. In this paper, we report our experience developing and deploying the Intelligent Online Selling Point Extraction (IOSPE) system to serve the recommendation system in the JD.com e-commerce platform. Since July 2020, IOSPE has become a core service for 62 key categories of products (covering more than 4 million products). So far, it has generated more than 1.1 billion selling points, thereby significantly scaling up the selling point creation operation and saving human labour. These IOSPE generated selling points have increased the click-through rate (CTR) by 1.89% and the average duration the customers spent on the products by more than 2.03% compared to the previous practice, which are significant improvements for such a large-scale e-commerce platform.

Sleep stage recognition is crucial for assessing sleep and diagnosing chronic diseases. Deep learning models, such as Convolutional Neural Networks and Recurrent Neural Networks, are trained using grid data as input, making them not capable of learning relationships in non-Euclidean spaces. Graph-based deep models have been developed to address this issue when investigating the external relationship of electrode signals across different brain regions. However, the models cannot solve problems related to the internal relationships between segments of electrode signals within a specific brain region. In this study, we propose a Pearson correlation-based graph attention network, called PearNet, as a solution to this problem. Graph nodes are generated based on the spatial-temporal features extracted by a hierarchical feature extraction method, and then the graph structure is learned adaptively to build node connections. Based on our experiments on the Sleep-EDF-20 and Sleep-EDF-78 datasets, PearNet performs better than the state-of-the-art baselines.

With the rapid development of various computing technologies, the constraints of data processing capabilities gradually disappeared, and more data can be simultaneously processed to obtain better performance compared to conventional methods. As a standard statistical analysis method that has been widely used in many fields, Independent Component Analysis (ICA) provides a new way for motion detection by extracting the foreground without precisely modeling the background. However, most existing ICA-based motion detection algorithms use only two-channel data for source separation and simply generate the observation vectors by decomposing and reconstructing the images by row, hence they cannot obtain an integrated and accurate shape of the moving objects in complex scenes. In this article, we propose a refined ICA algorithm for motion detection (RICA-MD), which fuses a larger number of channels than conventional ICA-based motion detection algorithms to provide more effective information for foreground extraction. Meanwhile, we propose four novel methods for generating observation vectors to further cover the diverse motion styles of the moving objects. These improvements enable RICA-MD to effectively deal with slowly moving objects, which are difficult to detect using conventional methods. Our quantitative evaluation in multiple scenes shows that our proposed method is able to achieve a better performance at an acceptable cost of false alarms.

A reliable recognition of human activities using IoT devices (e.g., on-body wearable sensors) enables various applications, such as fitness tracking, bad habit detecting, healthcare support and elder care support. However, inaccurate results may cause an adverse effect on users or even an unpredictable accident. In order to improve the accuracy in the daily life activities classification, we propose in this paper countable and uncountable activities to better facilitate the understanding of the nature of daily life activities. We design global and local features and their integrated feature set for classifying countable and uncountable activities. The key idea is to examine human daily life activities from different perspectives and attempt to give a comprehensive description of the characteristics of each activity through leveraging the global and local features. By using only one simple accelerometer, our approach is evaluated to be able to recognize daily life activities with higher accuracy than the state of the art, based on one self-collected and another public available dataset.

Detecting difference between two process models is a recurrent operation in business process management. A process model has multiple features, such as structure, behavior, and resource. Most of the existing methods only focus on one feature, which results in the loss of information in terms of other features. To provide more information on process difference to users, this paper proposes KS-Diff which can detect both structural and behavioral differences between two process models. First, the process models are transformed into their corresponding task-based process structure trees (TPSTs). Then, the one-hot codes are used to encode all leaf nodes of TPST, and the non-leaf nodes are encoded by the combination of one-hot codes of their child nodes. Next, the common key structure of two process models is extracted based on the one-hot encoding. Finally, the structural and behavioral differences are extracted on the basis of this common key structure. The efficiency study is provided to show the efficiency of KS-Diff.

Human activity recognition plays a key role in the application areas such as fitness tracking, healthcare and aged care support. However, inaccurate recognition results may cause an adverse effect on users or even an unpredictable accident. In order to improve the accuracy of human activity recognition, multi-device and deep learning based approaches have been proposed. However, they are not practical on a daily basis due to the limitations that devices are difficult to wear, and deep learning requires large training dataset and incurs expensive computational costs. To address this problem, we propose a novel approach, multiscale feature engineering for human activity recognition (MFE-HAR), which exploits the properties of arm movement from global and local scales using the accelerometer and gyroscope sensors on a single wearable device. Our method takes advantage of having important features at multiple scales over previous single-scale methods. We evaluated the performance of the proposed method on two public datasets and achieved the mean classification accuracy of 93% and 98% respectively. Our proposed system performs better than the state of the art multi-device based approaches, and is more practical for real-world applications.

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

A clock mesh planning and synthesis method is proposed which significantly reduces the power dissipation on the network while considering the power density and timing slack simultaneously. The proposed method is performed at the postplacement stage and consists of three major steps: 1) feasible moving region construction of each register considering timing slack; 2) mesh grid wire generation and placement; and 3) incremental register placement for stub wire minimization considering power density and timing slack. The advantages of the proposed method are the reduced power dissipation-28% on average on the benchmark circuits-the optimized power density, and the guaranteed nonnegative timing slack. These advantages are possible through a decreased timing slack (1.1% of the clock period) and change in the logic wirelength (+5.9%) on the benchmark circuits.

This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts xor gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the xor gates can be reconfigured for different modes of clock gating (sleep mode, busy mode, etc.) such that a mode-specific reduction of the peak current can be achieved. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% by assigning polarity to xor gates at the sink level of the clock tree. An additional 12.8% reduction in the worst case peak current can be achieved by reconfiguring the polarity assignment based on the clock gating information. The proposed flow increases the area by 7.1% but reduces both the total power consumption by 23.8% and the global skew increase (due to polarity assignment) from 19.3 to 8.8 ps. The insertion of xor gates at the non-sink nodes is also studied to further reduce the global skew increase and the area overhead.

A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. In the proposed method, a forest of steiner trees is first created which connects the registers so as to achieve zero skew and greedily balance the total capacitance of each tree. Then, a balanced assignment of the steiner trees to the tapping points is performed to guarantee a balanced capacitive load on the rotary network. The proposed routing method is tested with the ISPD clock network contest and IBM r1-r5 benchmarks. The experimental results show that the capacitive load imbalance is very limited. The total wirelength is reduced by 64.2% compared to the best previous work known in literature through the combination of steiner tree routing and the assignment of trees to the tapping points. The average clock skew simulated using HSPICE is only 8.8ps when the bounded skew target is set to 10.0ps.

This paper presents a topology design-based solution that addresses one of the major challenges in the design of Rotary Traveling Wave Oscillator (RTWO) based clock networks-the direction of oscillation. A “rotary oscillator array (ROA) brick” structure is proposed that guarantees the consistency of the rotation direction of the traveling signals on all the RTWO rings in an ROA. The ROA built from ROA bricks has the following advantages: (1) The same phase point of all the RTWO rings in the array can easily be tracked, (2) The same phase points of the ROA are independent of the specific rotation direction of the traveling signals on the ROA. SPICE simulations demonstrate these advantages of the brick-based ROA circuit design in establishing the directional consistency of the RTWO rings.

A clock mesh network synthesis and optimization flow is proposed which entails the optimal mesh size selection, incremental register placement, mesh reduction and buffer driver insertion. The proposed method is based on incrementally placing the registers on a mesh, which gives the method its name "Register on MEsh (ROME)". The primary objectives of ROME are low global clock skew and power dissipation, which are achieved through a sparse mesh implementation with registers mesh. Experimental results show that the total wirelength on the clock mesh (grid wires and stub wires) is reduced by 36.1% with a 2.8ps clock skew improvement. The total power consumption of the experimented circuits is reduced by 14.1% on average.

This paper presents a novel clock polarity assignment method to reduce the peak current on the vdd/gnd rails of a clock-gated integrated circuit. The proposed method inserts XOR gates at one level of the clock tree to facilitate the polarity assignment with limited skew degradation. The polarity of clock buffers are configured during runtime such that a maximal peak current reduction is obtained after clock gating. The method is integrated into an industrial design flow to study the practicality. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% and 33.9% by inserting XOR gates at the sink level and non-sink level of the clock tree, respectively. Additional 12.8% and 12.9% reductions in the worst case peak current for a clock tree with XOR gates inserted at the sink and non-sink level, respectively, can be achieved by reconfiguring the polarity assignment during runtime based on the clock gating information.

A novel clock mesh network synthesis approach is proposed in this paper which generates an improved mesh size with registers placed incrementally considering the timing slack on the data paths and the non-uniform grid wire placement. The primary objective of the method is to reduce the power dissipation without a global skew degradation, which is achieved through a sparse and non-uniform mesh implementation with registers incrementally placed in close vicinity to the mesh grids. The incremental register placement is based on the timing information in order to preserve the timing slack of the circuit. Experimental results show that the total wirelength (mesh grid wires and stub wires) as well as the power dissipation is reduced significantly on the clock mesh network. Specifically, the wirelength of the mesh network and the power dissipation of the clock network are reduced by 52% and 48% on average, respectively. Moreover, the global clock skew and the non-negative timing slack are preserved.

A clock polarity assignment method is proposed that reduces the peak current on the vdd/gnd rails of an integrated circuit. The impacts of (i) the output capacitive load on the peak current drawn by the sink-level clock buffers, and (ii) the buffer/inverter replacement scheme of polarity assignment on timing accuracy are considered in the formulation. The proposed sink-level-only polarity assignment is performed by a lexi-search algorithm in order to balance the peak current on the clock tree. Most of the previous polarity assignment methods that do not include clock tree resynthesis lead to an undesirable increase in the worst corner clock skew. Hence, a skew-tuning scheme is proposed that reduces the clock skew through polarity refinement and not through clock tree resynthesis. The proposed polarity assignment method with the skew-tuning scheme is implemented within an industrial design flow for practicality. Experimental results show that the worst-case peak current drawn by the clock tree can be reduced by an average of 36.5%. The worst corner clock skew is increased from 60.7ps to 76.2ps by applying the proposed polarity assignment method. The proposed skew-tuning scheme reduces the worst-case clock skew from 76.2ps to 61.5ps, on average, with a limited degradation in the peak current improvement (36.5% to 31.2%, on average).