This work presents a lightweight, fully digital, unsupervised calibration method for SAR ADCs that directly targets harmonic distortion without relying on costly FFT or supervised training techniques. Distortion is estimated from a small, configurable set of harmonic bins using a time-multiplexed fixed-point Goertzel engine, such that the objective-function cost scales linearly with the number of tracked harmonic spurs, remains independent of the acquisition length, and decouples calibration memory from the number of acquired samples. A particle swarm optimizer then updates a decoder that re-maps raw SAR codes to calibrated reconstruction levels under bounded constraints. Guided by a distortion-based quantizer view that clarifies the role of non-invasive code re-interpretation, the proposed method removes converter distortion with negligible overhead, requiring only a 56 B LUT decoder and an adder tree. Measurements on 50 MS/s differential SAR ADC in 22 nm FD-SOI across five chip instances show that, with K=28 tracked harmonics, |THD| improves from 68.15 dB up to 78.04 dB (+9.89 dB), demonstrating best-in-class harmonic spur suppression up to the quantization noise limit, outperforming the SotA across PVT variations and input frequencies, while maintaining sub-mW power consumption.

This work presents a fully integrated, low-noise, CMOS reference generator capable of operating at supply voltages from 0.7 V up to 1.5 V. A 3-phase barrel shifting technique is proposed to upconvert the flicker noise, achieving an integrated noise of 19.7 μVrmsover a 10 kHz bandwidth under typical conditions (0.7 V, 27 °C), without needing bulky off-chip filters. The untrimmed reference voltage from post-layout simulations exhibits an average temperature drift of 30 ppm/°C across the full temperature range of -40 °C to 125 °C. A 2-stage switched-capacitor notch filter that is proposed, brings a 60-fold reduction in the upconverted voltage ripple, and a 40 dB reduction in thermal noise at 10kHz while resulting in an exceptional Power Supply Rejection Ratio (PSRR) of -95 dB at 50 Hz. The circuit is implemented in a 22-nm FDSOI process, occupying an area of only 0.01 mm2while consuming a power of 288 nW at the typical condition.