Sanjay Moulik

dblp:88/11258 · DBLP profile ↗
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23ranked-venue papers
10as first author
16since 2021 · last 2026
0000-0003-3654-781XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 9 · 5 first-author · 8 since 2021Applied, interdisciplinary, general and emerging computing · 8 · 3 first-author · 4 since 2021Human-computer interaction and ubiquitous computing · 6 · 3 first-author · 3 since 2021Security and privacy · 2 · 1 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
YearPublicationVenuePosition
2026 SAMIT: Secure Multi-Authority Access Control with Dynamic Attribute Updates for Embedded IoT-CPS
abstract
In today’s world, Cyber-Physical Systems (CPS) play a key role in areas like smart homes, transportation, and healthcare, where lightweight IoT devices are used to monitor and control activities. As the number of IoT devices keeps growing, so does the amount of data they generate. This calls for scalable computing and storage solutions, which are often provided using fog and cloud technologies. However, applying secure and efficient access control in these decentralized and resource-limited environments is still a major challenge. Ciphertext-Policy Attribute-Based Encryption (CP-ABE) allows fine-grained access control, but existing multi-authority schemes do not support dynamic update in user attributes–something that is important in real-life CPS, where user roles often change. Also, the heavy computations required in CP-ABE can slow down low-power IoT devices. To solve these issues, we propose SAMIT , a CP-ABE scheme with multiple authorities that supports efficient attribute updates and is designed for embedded systems. Our scheme uses fog nodes to handle complex computations, reducing the load on resource-constrained IoT devices. Security and performance results show that SAMIT is secure and suitable for CPS with limited device resources.
Richa Sarma, Sanjay Moulik
ACM Trans. Embed. Comput. Syst.2
2025 ECO-FAST: An Energy Cognizant Fault-Tolerant Scheduler for Heterogeneous Computing Systems
Sanjay Moulik, Richa Sarma
DS-RT1
2024 SMAC: A Secure Multi-authority Access Control Scheme with Attribute Unification for Fog Enabled IoT in E-Health
Richa Sarma, Sanjay Moulik, Akangjungshi Longkumer
PDCAT2
2024 FRESH: Fault-tolerant Real-time Scheduler for Heterogeneous multiprocessor platforms
Sanjay Moulik, Yanshul Sharma
Future Gener. Comput. Syst.1
2024 e-SAFE: A secure and efficient access control scheme with attribute convergence and user revocation in fog enhanced IoT for E-Health
Richa Sarma, Sanjay Moulik
J. Inf. Secur. Appl.2
2024 TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores
abstract
The recent shift in the VLSI industry from conventional MOSFET to FinFET for designing contemporary chip-multiprocessor (CMP) has noticeably improved hardware platforms’ computing capabilities, but at the cost of several thermal issues. Unlike the conventional MOSFET, FinFET devices experience a significant increase in circuit speed at a higher temperature, called temperature effect inversion (TEI), but higher temperature can also curtail the circuit lifetime due to self-heating effects (SHEs). These fundamental thermal properties of FinFET introduced a new challenge for scheduling time-critical tasks on FinFET-based multicores that how to exploit TEI towards improving performance while combating SHEs. In this work,TREAFET, a temperature-aware real-time scheduler, attempts to exploit the TEI feature of FinFET-based multicores in a time-critical computing paradigm. At first, the overall progress of individual tasks is monitored, tasks are allocated to the cores, and finally, a schedule is prepared. By considering the thermal profiles of the individual tasks and the current thermal status of the cores, hot tasks are assigned to the cold cores and vice-versa. Finally, the performance and temperature are balanced on-the-fly by incorporating a prudential voltage scaling towards exploiting TEI while guaranteeing the deadline and thermal safety. Moreover,TREAFETstimulates the average runtime frequency by employing an opportunistic energy-adaptive voltage spiking mechanism, in which energy saving during memory stalls at the cores is traded off during the time slice having the spiked voltage. Simulation results claimTREAFETmaintains a safe and stable thermal status (peak temperature below 80 °C) and improves frequency up to 17% over the assigned value, which ensures legitimate time-critical performance for a variety of workloads while surpassing a state-of-the-art technique. The stimulated frequency inTREAFETalso finishes the tasks early, thus providing opportunities to save energy by power gating the cores, and achieves a 24% energy delay product (EDP) gain on average.
Shounak Chakraborty 0001, Yanshul Sharma, Sanjay Moulik
ACM Trans. Embed. Comput. Syst.3
2023 Relevance of ISO/SAE 21434 in Vehicular Architecture Development
abstract
Research in terms of security in vehicular architecture has been a focal point of deliberation in the automotive sector. The Automotive industry development has continuously evolved the scenario of adding more integration to networked vehicles or semi-autonomous vehicles. The end product of such manufacturing practices is a vehicle becoming a networked computer on wheels. In spite of providing numerous advantages, these developments in the automotive industry are also bringing more challenges in terms of security. Hence, the industry has been forced to emphasise the principle of Security by Design. Efforts in this direction have resulted in the formulation of the ISO/SAE 21434 standard. In this work, we focus on summarising the ISO/SAE 21434 standard and analysing its relevance for automotive architecture development. Related works in the standard's approach of Security by Design are summarised. Additionally, we propose an application work of the standard in the context of automotive Architecture development as future work.
V. Kethareswaran, Sanjay Moulik
SMC2
2023 An Interplay of Energy and Temperature Minimization Techniques for Heterogeneous Multiprocessor Systems
abstract
Real-time embedded systems are designed to perform specific functions in real-time, with a microcontroller, memory, and input/output devices. The scheduler is a critical component that manages resource allocation and schedules jobs based on priority and available resources. Multiprocessor platforms improve performance, scalability, redundancy, and flexibility, with different approaches to scheduling, such as global, partitioned, and semi-partitioned. Minimizing dynamic energy consumption and processor temperatures is essential for improving battery life and reliability and meeting power and thermal constraints in applications such as mobile devices, aerospace, and defense systems. There are many energy and temperature management techniques, but their effect on each other has not been studied in detail. Hence, we want to employ a few of those techniques and want to observe their impacts. In this work, we first propose a basic semi-partitioned scheduler for heterogeneous multiprocessor systems which supports the execution of real-time jobs. Then, we apply well-known energy and temperature minimization techniques over the proposed scheduler to study their impact on the system. To conduct our experiments, we use benchmark programs whose characteristics have been extracted using various simulators.
Yanshul Sharma, Sanjay Moulik
TENCON3
2022 RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore
abstract
In this work, we propose RESTORE that exploits the unique thermal feature of FinFET based multicore platforms, where processing speed increases with temperature, in the context of time-criticality to meet other design constraints of real-time systems. RESTORE is a temperature aware real-time scheduler for FinFET based multicore system that first derives a task-to-core allocation, and prepares a schedule. Next, it balances the performance and temperature on the fly by incorporating a prudential temperature cognizant voltage/frequency scaling while guaranteeing task deadlines. Simulation results claim, RESTORE is able to maintain a safe and stable thermal status (peak temperature below 80°C), hence the frequency (3.7 GHz on an average), that ensures legitimate time-critical performance for a variety of workloads while surpassing state-of-the-arts.
Yanshul Sharma, Sanjay Moulik, Shounak Chakraborty 0001
DATE2
2022 ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms
Yanshul Sharma, Shounak Chakraborty 0001, Sanjay Moulik
J. Supercomput.3
2021 TEFRED: A Temperature and Energy Cognizant Fault-Tolerant Real-Time Scheduler Based on Deadline Partitioning for Heterogeneous Platforms
Yanshul Sharma, Zinea Das, Sanjay Moulik
PDCAT3
2021 Invalid Scenarios of External Cluster Validity Indices: An Analysis Using Bell Polynomial
abstract
External cluster validity indices (CVIs) are used to evaluate various clustering algorithms by comparing the obtained clustering result with the gold standard. These indices provide some values for the obtained clustering result, indicating how good or bad the obtained clustering result is compared to the gold standard. For an external CVI, it is desirable to always provide the values within its range; otherwise, the clustering result cannot be correctly interpreted. Thus, in this work, our objective is to theoretically obtain the scenarios where these indices are unable to provide valid values. 26 commonly used indices identified in the existing literature are considered for our analysis purposes. For all these CVIs, we are able to determine the scenarios where these indices provide undefined values. Using the Bell number and Bell polynomial notion, we have attempted to represent the number of such scenarios.
Sumit Mishra, Sanjay Moulik, Ved Prakash
SMC2
2021 SMART-EDF: An EDF based semi-partitioned energy-aware multicore scheduler for real-time systems
abstract
In real-time systems, schedulers have to perform tasks with a specific degree of urgency; otherwise, it may lead to significant damage. Additionally, modern systems also want to focus on other design criteria like providing high system utilization, executing tasks with a low energy budget etc., making the job of a scheduler more challenging in such systems. EDF is one of the first optimal schedulers designed for single-core real-time systems, and since then, it has remained in the focus of the research fraternity. Unfortunately, it is not suitable for multicore platforms. In this paper, we have designed a semi-partitioned energy-aware scheduler for real-time systems based on EDF. Initially, the proposed scheduler uses the strategy of deadline partitioning to make the algorithm semi-partitioned. Then, it applies EDF to schedule the tasks on available cores. Next, it carefully schedules tasks that require migration across multiple cores. At last, it scales the frequency of individual cores based on the workload assignment of previous steps. Our experimental analysis shows that the proposed scheduler can provide high resource utilization (unlike traditional multicore schedulers) and reduce dynamic energy consumption (up to 8.94% on an average) of the systems.
Yanshul Sharma, Sanjay Moulik
TENCON2
2021 RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems
Sanjay Moulik
Integr.1
2021 SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorEReal-time Systems
Sanjay Moulik, Zinea Das, Rajesh Devaraj, Shounak Chakraborty 0001
J. Syst. Archit.1
2021 TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler
Sanjay Moulik, Arnab Sarkar 0001, Hemangee K. Kapoor
J. Syst. Archit.1
2020 EA-HRT: An Energy-Aware scheduler for Heterogeneous Real-Time systems
abstract
Developing energy-efficient schedulers for real-time heterogeneous platforms executing periodic tasks is an onerous as well as a computationally challenging issue. This research presents a heuristic strategy named, EA-HRT, for DVFS based energy-aware scheduling of a set of periodic tasks executing on a heterogeneous multicore platform. Initially it calculates the execution demands of every task on each of the different type of cores. Then, it simultaneously allocates each task on available cores and selects operating frequencies for the concerned cores such that the summation of execution demands of all tasks are met as well as there is minimum change in energy consumption for the system. Experimental results show that our proposed strategy is not only able to achieve appreciable energy savings with respect to state-of-the-art (2% to 37% on average) but also enables significant improvement in resource utilization (as high as 57%).
Sanjay Moulik, Rishabh Chaudhary, Zinea Das, Arnab Sarkar 0001
ASP-DAC1
2020 CEAT: A Cluster based Energy Aware Scheduler for Real-Time Heterogeneous Systems
abstract
Modern real-time systems based on heterogeneous multicore platforms can efficiently meet the disparate and high computation needs of the applications. The management of energy has become a topic of an incredible enthusiasm for analysts and practitioners during the past few years. Hence, this research presents a heuristic strategy named, CEAT, for energy-aware scheduling of a set of real-time periodic tasks on a DVFS enabled heterogeneous multicore platform. The presented strategy operates in three stages, namely Deadline Partitioning, Task-to-Core Allocation, and Energy-Aware Scheduling. Our experimental analysis shows that CEAT is not only able to successfully schedule more task sets (as high as 3.44% and 21.83%) compared to state-of-the-art [1] but also improve energy savings in the system.
Sanjay Moulik, Zinea Das, Gitimoni Saikia
SMC1
2020 TEARS: A temperature-aware real-time scheduler for heterogeneous multi-core systems
abstract
Nowadays, multi-core processing systems have to perform complex functionalities on densely packed multi-million gate platforms, which makes such systems prone to uncontrolled surges in core temperatures, if not effectively controlled. Increasing temperature above specified limits not only leads to high cost of cooling but also results in higher dissipation of leakage power together with a reduction in performance and lower system life expectancy. In this work, we propose a two-level low-overhead proportional fair resource allocation strategy called TEARS: A temperature-aware real-time scheduler for heterogeneous multi-core systems, for scheduling of periodic tasks with bounded number of migrations and context-switches. The proposed algorithm's first level divides time into distinct windows based on deadlines of tasks, so that exact proportional fairness is maintained at all window boundaries. The second level accomplishes intra-window scheduling with the aim of maximising the use of resources while not breaching a specified thermal threshold. Our experimental analysis shows that the presented strategy not only improves upon the state-of-the-art in terms of resource utilisation (as high as 16.09%) but also reduces average temperatures of cores in the system.
Yanshul Sharma, Richik Chanda, Sanjay Moulik
SMC3
2020 TA-HRT: A temperature-aware scheduler for heterogeneous real-time multicore systems
abstract
Over the years, the nature of processing platforms is witnessing a significant shift in most of the battery supported real-time systems, which currently underpins a blend of specific multicores to satisfy the needs of present day applications. Devising temperature-aware schedulers has become a critical issue for such kind of systems. Hence, this research presents a heuristic strategy named TA-HRT, for temperature-aware scheduling of a set of real-time periodic tasks on a heterogeneous multicore platform. The presented strategy operates in three stages, namely Deadline Partitioning, Core Clustering and Temperature-Aware Task Scheduling. Our experimental analysis shows that the presented strategy not only improves upon the state-of-the-art [1] in terms of resource utilisation (as high as 10.71%) but also reduces average temperatures of cores in the system.
Yanshul Sharma, Zinea Das, Alok Das, Sanjay Moulik
TrustCom4
2019 TASOR: A Temperature-Aware Semi-Partitioned Real-time Scheduler
abstract
Modern multicore systems, which execute complex functionalities on densely packed multi-million gate platforms, are often prone to unacceptable surges in core temperatures. Increase in temperature in such systems not only results in high cooling costs but also leads to high leakage power dissipation, along with reduced efficiency and lower life-span for the system. Given, a set of periodic real-time tasks to be executed on a thermally constrained multicore system, proportional fair schedulers form an attractive scheduling alternative. This is because of their flexibility and the ability to deliver efficient resource utilization, which can potentially enable accurate control over the timeliness of all tasks as well as stipulated temperature upper bounds on all processing cores, over the entire schedule length. In this paper, we propose a low-overhead three-level hierarchical temperature-aware semi-partitioned proportional fair scheduler, called Temperature-Aware Semi-partitioned Real-Time Scheduler (TASOR). The first level in TASOR partitions, time into discrete slices based on task deadlines, such that accurate proportional fairness is maintained at all slice boundaries. In the second level, it classifies each task as either hot or cool, based on it's temperature characteristics. At the last level, TASOR performs intra-slice scheduling with the objective of maximizing resource utilization. Our experimental results show that TASOR is able to perform appreciably under various realistic scenarios.
Sanjay Moulik, Zinea Das
TENCON1
2018 COST: A Cluster-Oriented Scheduling Technique for Heterogeneous Multi-cores
abstract
Development of efficient resource allocation strategies for real-time tasks on heterogeneous platforms has traditionally proved to be a challenging as well as a computationally expensive problem. However, strategies which can efficiently schedule real-time task sets on generic heterogeneous platforms having an arbitrary number of processor types, are rare. Most of the existing strategies are oriented towards systems with restricted number of processing core types. Hence, this paper proposes an effective low-overhead heuristic approach called COST, for scheduling a set of periodic tasks executing on a heterogeneous multi-core system. The proposed strategy works in three-phases namely, Core Clustering, Task Partitioning, and Task Scheduling. The Core Clustering step attempts to combine the available processing cores into a group of clusters. Each cluster consists of two cores and a disjoint subset of the given task set is assigned to it. The tasks assigned to a cluster are then allocated to the processing cores of the cluster and scheduled in a fair manner. Experimental studies show that our proposed scheme provides high resource utilisation with satisfactory acceptance ratios for a wide-range of task sets.
Sanjay Moulik, Rajesh Devaraj, Arnab Sarkar 0001
SMC1
2017 A Deadline-Partition Oriented Heterogeneous Multi-Core Scheduler for Periodic Tasks
abstract
Real-time systems are increasingly being implemented on heterogeneous multi-core platforms to efficiently cater to their diverse and high computation demands. Over the years, researchers have developed mechanisms to efficiently schedule tasks on homogeneous multi-cores such that all tasks meet their execution and deadline requirements. However, devising an efficient scheduling strategy for real-time tasks on heterogeneous platforms has proved to be a challenging as well as computationally expensive problem. Today, there is a severe dearth of low-overhead techniques towards real-time scheduling on heterogeneous platforms. Hence, we propose an effective low-overhead heuristic approach for scheduling a set of periodic tasks executing on a heterogeneous multi-core platform. Employing the concept of deadline partitioning to obtain a set of discrete time slices, we propose a scheme to efficiently schedule tasks over these time slices while incurring low and bounded number of migrations. Conducted experiments have shown promising results and indicate to the practical efficacy of our approach.
Sanjay Moulik, Rajesh Devaraj, Arnab Sarkar 0001, Arijit Shaw
PDCAT1