A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator

This paper describes key points and experimental validation in the development of a bottom--up hierarchical, multi--objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous--time ΔΣ A/D converter for WLAN applications, to generate a set of Pareto--optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto--optimal performance solutions of the hierarchical lower--level sub--blocks to generate the overall Pareto--optimal set at system level. The way the lower--level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom--up methodology. The experimental results validate the methodology for a 7--block hierarchical decomposition of a complex high--speed ΔΣ A/D modulator for a WLAN 802.11a/b/g standard.

A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm2

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as the exponent set of the posynomial expression are determined based on SPICE simulation data with device-level accuracy. We prove that this problem corresponds to solving a non-convex optimization problem without local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows the automatic generation of an accurate sizing model that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities and effectiveness of the presented modeling technique.

This paper presents a new, frequency-domain based method for modeling and analysis of phase-locked loop (PLL) small-signal behavior, including time-varying aspects. Focus is given to PLLs with sampling phase-frequency detectors (PFDs) which compute the phase error only once per period of the reference signal. Using the harmonic transfer matrix (HTM) formalism, the well known continuous-time, linear time-invariant (LTI) approximations are extended to take the impact of time-varying behavior arising from the sampling nature of the PFD, into account. Especially for PLLs with a fast feedback loop, this time-varying behavior has severe impact on, for example, loop stability and cannot be neglected. Contrary to LTI analysis, our method is able to predict and quantify these difficulties. The method is verified for a typical loop design.

This paper presents an overview of methods to automatically generate posynomial response surface models for the performance characteristics of analog integrated circuits based on numerical simulation data. The methods are capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics, at SPICE-level accuracy. This approach allows for automatic generation of an accurate sizing model for a circuit that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming and approximate nature of handcrafted analytic model generation. The methods are based on techniques from design of experiments and response surface modeling. Attention is paid to estimating the relative "goodness-of-fit" of the generated models. Experimental results illustrate the capabilities and effectiveness of the presented methods.

Microelectromechanical systems (MEMS) components are gradually finding their way in communication applications. To fully understand their behavior in electrical circuits, an interpretable model is required that, in addition, can be simulated efficiently. This paper presents a model for a MEMS variable capacitor (varicap), that can be evaluated much more efficiently and equally accurate during circuit simulation than the differential equations that are normally used to describe this component. The model, based on Volterra series, describes the frequency dependence (e.g., the mechanical resonance) in combination with the nonlinear behavior of the MEMS varicap. The model is simple enough such that it can be interpreted by designers who want to use the MEMS varicap in RF communication circuits.

This paper presents a method for constructing behavioral models for harmonic oscillators and sets of coupled harmonic oscillators. These models are useful for system-level simulations and tradeoff analysis. The modeling method allows capturing the steady-state and transient behavior of the target oscillators through a sequence of transformations of the circuit equations. Model extraction is based on ideas of perturbation analysis and averaging. The resulting models are evaluated at a computational cost that is well below that of solving the original circuit equations. Another major advantage of the approach is the explicit separation of the slow- and fast-varying components of the oscillator's behavior. This allows using a much larger time step during numerical simulations. The technique is illustrated for both a single harmonic oscillator and a harmonic quadrature oscillator.

This paper presents an new direct--fitting method to generate posynomial response surface models with arbitrary constant exponents for linear and nonlinear performance parameters of analog integrated circuits. Posynomial models enable the use of efficient geometric programming techniques for circuit sizing and optimization. The automatic generation avoids the time--consuming nature and inaccuracies of handcrafted analytic model generation. The technique is based on the fitting of posynomial model templates to numerical data from SPICE simulations. Attention is paid to estimating the relative `goodness--of--fit' of the generated models. Experimental results illustrate the significantly better accuracy of the new approach.

A new approach is presented for the construction of behavioral models for harmonic oscillators and sets of coupled harmonic oscillators. The models can be used for system-level simulations and trade-off analysis. Besides the steady state behavior, the model also takes the transient behavior of the oscillation amplitudes and phase differences into account. This behavior is modeled using a set of linear differential equations. Their extraction from a netlist description is based upon the ideas of perturbation analysis and stochastic averaging. The modeling equations are valid in the neighbourhood of the oscillator's steady-state operating point and can be evaluated at very low computational cost. Another major advantage of the approach is that it explicitely separates the fast-varying steady-state behavior and the slow varying transient behavior. This allows for straightforward application of multi-rate simulation techniques, greatly boosting simulation speeds. The technique is illustrated for a quadrature oscillator.

This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a template-based fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the generated expressions enables the use of efficient geometric programming techniques when using these expressions for circuit sizing and optimization. Attention is paid to estimating the relative 'goodness-of-fit' of the generated expressions. Experimental results illustrate the capabilities of the approach.

A new technique is presented for generating symbolic expressions for the harmonic transfer functions of linear periodically time-varying (LPTV) systems, like mixers and PLL's. The algorithm, which we call Symbolic HTM, is based on the organisation of the harmonic transfer functions into a harmonic transfer matrix. This representation allows to manipulate LPTV systems in a way that is similar to linear time-invariant (LTI) systems, making it possible to generate symbolic expressions which relate the overall harmonic transfer functions to the characteristics of the building blocks. These expressions can be used as design equations or as parametrized models for use in simulations. The algorithm is illustrated for a downconversion mixer.

This paper describes the similarities and differences between two widely publicized methods for analyzing oscillator phase behavior. The methods were presented in [3] and [6]. It is pointed out that both methods are almost alike. While the one in [3] can be shown to be, mathematically, more exact, the approximate method in [6] is somewhat simpler, facilitating its use for purposes of analysis and design. In this paper, we show that, for stationary input noise sources, both methods produce equal results for the oscillator's phase noise behavior. However, when considering injection locking, it is shown that both methods yield different results, with the approximation in [6] being unable to predict the locking behavior. In general, when the input signal causing the oscillator phase perturbations is non-stationary, the exact model produces the correct results while results obtained using approximate model break down.

Presents a circuit simplification method for the symbolic analysis of a linear or linearized (small-signal) analog circuit. Its goal is to generate simplified signal flow graphs describing the circuit's behavior in well-defined frequency intervals. These frequency subranges are automatically constructed based on numerical calculation of the system's poles and zeroes. The circuit reduction has been implemented using graph manipulation techniques. The order in which these manipulations are applied is based on a tradeoff between the error and the level of simplification they introduce. The technique can be used to symbolically localize poles and zeroes and inspect their observability. This allows generating symbolic expressions for poles and zeroes, which in optimal conditions lead to simple, interpretable expressions. The technique can also be used as preprocessor to simplify a circuit before analyzing it with standard approximate symbolic analysis techniques. In that case, it helps overcoming the time and memory constraints related to those techniques. Experimental results show the effectiveness of the approach.

A methodology is presented for the physical design automation of array-type analog blocks such as encountered in high-speed data converters and other analog circuits. The approach takes into consideration typical analog constraints and offers full flexibility. A three-step procedure (floorplanning, symbolic routing, and technology mapping), of which the last two steps have been automated in a tool called Mondriaan, solves the layout synthesis problem in a fast and technology-independent way. A set of bus and tree device generators complements the tool set. Industrial-strength examples prove that the proposed solution speeds up the generation of high-quality analog layouts significantly.

This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics; are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.

This paper presents an algorithm for generating symbolic expressions for the harmonic transfer functions of linear periodically time-varying (LPTV) systems, like mixers and PLLs. The harmonic transfer functions characterize the up- and downconversion behavior of the wanted and unwanted signal components. The algorithm, which the authors call Symbolic HTM, is based on the organization of the harmonic transfer functions into a harmonic transfer matrix. This representation allows one to manipulate LPTV systems in a way that is similar to linear time-invariant systems, making it possible to generate symbolic expressions relating the overall harmonic transfer functions to the building block parameters. These expressions can be used as design equations or as parameterized models for use in simulations or synthesis. Comparison of the symbolic models with numerical data shows them to be accurate, even for small numbers of modeling terms.

This paper presents an efficient time-domain simulation approach for telecommunication frontends at architectural level. It is based upon the use of complex damped exponential modeling functions. These allow to construct accurate signal models for digitally modulated telecom signals, requiring only few modeling functions. Since these models are valid over a long range of time, they allow for a large timestep, which greatly speeds up time-domain simulation of the telecom frontends. Details of a simulation approach based upon this signal model are discussed. The approach is verified by experimental results.

This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enable the use of efficient geometric programming techniques for circuit sizing and optimization. To avoid manual derivation of approximate symbolic equations and subsequent casting to posynomial format, techniques from design of experiments and response surface modeling in combination with SPICE simulations are used to generate signomial and posynomial models in an automatic way. Attention is paid to estimating the relative 'goodness-of-fit' of the generated models. Experimental results allow one to assess both the quality of the generated models as well as the strengths and the limitations of the presented approach.

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5µm CMOS technology, which has been designed using a systematic design methodology for current-steering D/A converters. A flexible architecture is proposed for which the design parameters are calculated using a performance-driven top-down design methodology. The layout of the regular structure typical for D/A converters is automatically generated. Measurement results are reported. Due to the systematic design methodology, the design was realized in less than one month total accumulated person effort.

This paper presents an automated, layout-aware RF LC-oscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.

Since transistor mismatch directly affects the performances of a broad class of analog CMOS devices such as comparators, A/D and D/A converters, it is of the utmost importance to determine these parameters for every available CMOS technology. Nowadays, this is done by processing and evaluating a large number of especially designed test structures that have no further use. This paper presents a technique to extract the transistor mismatch parameters from the performance of a simple current-steering CMOS D/A converter.

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used as a standard reduction engine that ensures the validity of the resulting network model in a specific (set of) design point(s) within a given frequency range and a given magnitude and phase error. It can also be used as an analysis engine to extract symbolic expressions for poles and zeroes. The reduction technique is driven by analysis of the signal flow graph associated with the network model. Experimental results show the effectiveness of the approach. 1

The complete application of a hierarchical top-down design methodology to analog sensor interface front-ends is presented: from system-level specifications down to implementation in silicon, including high-level synthesis, analog block generation and layout generation. A new approach for implementing accurate and fast estimators for the different blocks in the architecture is described. These estimators provide the essential link between the high-level synthesis and the block generation in our hierarchical top-down methodology. The methodology is illustrated by means of the design of a complex and realistic example. Measurement results are included.

This paper describes a new DC modeling methodology applicable to CMOS integrated circuits. It is named operating point driven DC formulation because the operating point is specified directly, and the device dimensions W and L are determined out of it. With other methods, one specifies the device dimensions W and L and determines the operating point. Our method is important for manual design because it allows the designer to reason in terms of voltages and currents and releaves him from the burden of determining device sizes. The algorithm is guaranteed to converge, and is computationally efficient, which allows interactive design space exploration using optimization-based sizing. A design plan used in optimization-based sizing consists for the largest part out of solving the DC part. Speeding up the DC part with a computationally efficient algorithm, that allows parallellisation, results in a boost of optimization speed. I. Introduction DC modeling is a topic that received much atte...

New methods for analog fault detection and for the selection of measurements for analog testing (wafer probe or final testing) are presented. Using Bayes' rule, the information contained in the measurement data and the information of the a priori probabilities of a circuit being fault free or faulty are converted into a posteriori probabilities and used for fault detection in analog integrated circuits, with a decision criterion that considers the statistical tolerances and mismatches of the circuit parameters. An adaptive formulation of the a priori probabilities is given that updates their values according to the results of the testing and fault detection. In addition, a systematic method is proposed for the optimal selection of the measurement components so as to minimize the probability of an erroneous test decision. Examples of DC wafer-probe testing as well as production testing using the power-supply current spectrum are given that demonstrate the effectiveness of the algorithms.

This paper describes a new modeling methodology that allows to derive systematically behavioral signal path models of operational amplifiers. Combined with symbolic simulation, these models provide high qualitative insight into the small-signal functioning of a circuit. The behavioral signal path model provides compact interpretable expressions for the poles and zeros that constitute the signal path. These expressions show which design parameters have dominant influence on the position of a pole/zero and thus enable a designer to control a manual interactive sizing process. The methodology consists of the application of a sequence of abstractions, so that one gradually progresses from a full device to a full behavior circuit representation. During this translation, qualitative insight and design requirements are obtained. The methodology is implemented in an open tool called EF2ef. The behavioral signal path model is also used for optimization based sizing in order to achieve pole placement in an efficient way. For optimization based siting, a new strategy for hierarchical penalty function composition is proposed, which allows sequential pruning of the design space. Combined with an operating point driven DC formulation and local minimax optimization, a fast sizing method is obtained which can be used for interactive design space exploration. Experimental results of both modeling and siting are shown.

Article Free Access Share on Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies Authors: L. Richard Carley Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Georges G. E. Gielen Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium Electrical Engineering, Katholieke Universiteit Leuven, Leuven, BelgiumView Profile , Rob A. Rutenbar Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Willy M. C. Sansen Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium Electrical Engineering, Katholieke Universiteit Leuven, Leuven, BelgiumView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 298–303https://doi.org/10.1145/240518.240573Online:01 June 1996Publication History 36citation523DownloadsMetricsTotal Citations36Total Downloads523Last 12 Months21Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A new approach towards performance-driven placement of analog integrated circuits is presented. The performance speci cations directly drive the layout tools without intermediate parasitic constraints. A simulatedannealing algorithm is used to drive an initial solution to a placement that respects the circuit's performance speci cations. During each iteration, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool handles symmetry constraints, circuit loading e ects and device mismatches. The feasibility of the approach is demonstrated withapractical circuit example. 1. Overview The main concern in automated analog layout synthesis

A flexible and efficient program for the optimal sizing of analog integrated circuits is presented. The circuits are modeled with symbolic equations that are derived automatically by a symbolic simulator. The advantages and limitations of symbolic analysis for this application are investigated. Before optimization, the equations are ordered symbolically and then compiled in a way as minimize the overall evaluation time. The optimization tool then determines all device sizes and biasing for the circuit to meet the specifications while minimizing a user-defined cost function. Experimental results on realistic analog circuits show the efficiency of the approach.

The aim of this forum session is to stimulate a discussion and an exchange of ideas on the advantages and disadvantages of symbolic analysis. The focus of the discussion is on the feasibility of the symbolic approaches in circuit design and the role they can and/or cannot play in the circuit CAD world.>

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.>

A novel method for the fault detection of analog circuits is proposed. Simple measurements are used to detect the possible faults in an analog circuit. Bayes decision rule is applied to combine the priori information and the information from testing. A sequential method to evaluate the value of the priori probability is given. Principle component analysis is applied for the calculation of the discrimination function in the case of the measurements being dependent. Examples are given to demonstrate the efficiency and the effectiveness of the algorithm.>

This tutorial paper gives an overview of the history and present state of the art in symbolic analysis of electronic circuits at the so-called circuit level. Symbolic analysis is defined as a technique generating a closed-form analytic expression for a circuit characteristic with the circuit's elements represented by symbols. Such analytic information complements the results from numerical simulations. The paper then describes the different application areas of symbolic analysis for the design of analog circuits. Symbolic analysis is mainly used as a means to obtain insight into a circuit's behavior, to generate analytic models for automated circuit sizing, and in applications requiring the repetitive evaluation of circuit characteristics. Next, the present capabilities and limitations of symbolic analysis, both in functionality and efficiency, are discussed. The major symbolic analysis methods are presented, and algorithmic details are provided for symbolic approximation, hierarchical decomposition, and symbolic distortion analysis. Finally, existing symbolic simulators are compared, and directions for future research are pointed out.>

A high-frequency (HF) small-signal model is presented that is capable of describing accurately the MOS transistor (in saturation) at frequencies beyond the cutoff frequency. The model is carefully compared to other models. It is shown how all the circuit elements of the model can be measured. This measurement method uses S-parameter measurements, computer-controlled calibration techniques of the test setup and network analyzer, mathematical transformations of the S-parameters to other linear parameters, and extraction routines to fit the data towards the HF model. The model is finally used in the design of an HF optical transconductance amplifier to prove that this model is much more accurate than the classical models at higher frequencies.>

A new routing algorithm is presented which is based on the expansion of a line in the direction perpendicular to the line. The line-expansion principle is first applied to the single layer routing problem. For the routing on two layers only some minor modifications have to be made. An important extension is added in which the search for an interconnection from a given point is initiated in more than one direction at the same time. The major advantage of the line-expansion algorithm over the well-known line-search algorithm is the guarantee that always a solution will be found if one exists.