With the progressive augmentation of the density of 3-D processor arrays, some processor elements (PEs) often fail due to overload or overheating during massively parallel computing operations. Therefore, it is necessary to take effective fault-tolerant technology to ensure the reliability of the system. This article investigates an efficient reconfiguration method to construct 3-D fault-free logical subarray with more fault-free PEs and less interconnection length (interlength). First, we propose a novel method based on the barrel effect to find the bottleneck plane of 3-D processor arrays. Second, an efficient compensation strategy is proposed to replace faulty PEs on adjacent physical planes with fault-free PEs on the bottleneck planes, which leads to more fault-free PEs that can be used to construct the subarray. Then, we propose a heuristic to construct the subarray and optimize iteration redundancy to accelerate reconstruction. Finally, a heuristic optimization algorithm is proposed to reduce the interlength between PEs, which can reduce the dynamic power consumption and communication costs. In addition, we propose a more accurate method to calculate the lower bound of the interlength to better evaluate the performance of the algorithm. Simulation experiments show that, compared to the state-of-the-arts, on$128\times 128\times 128$host array, the utilization rate of fault-free PEs can be improved up to 15.6% and the interlength redundancy can be reduced by 78.2% for random faults. On$64\times 64\times 64$host array, the average improvement of the two indicators under clustered faults can reach 93.2% and 69.3%. Moreover, for all cases considered, the proposed new lower bound and reconstruction time can be reduced by an average of 18.47% and 76.13%, respectively.

Sensors in wireless sensor network (WSN) are usually deployed in the wild or even hostile circumstance. What is worse, most of the sensors have limited communication bandwidth, computation resources and energy. Therefore, it is challenging to ensure the security of WSN without decreasing its network performance. Network coding (NC) is a promising way for improving communication capability in WSN, e.g., high throughput, robustness and low-energy. Nevertheless, network coding is vulnerable to malicious attacks. Presently, many secure detections, such as information theoretic-based or cryptographic-based techniques, have been proposed to deal with a single type of attack, but are incapable of resisting the joint attacks, e.g., the union of pollution attacks and replay attacks. In this paper, a secure detection service is presented. It is deployed on every node of WSN to monitor, manage and control the messages passing through them in real-time. In the service, a lightweight timestamp-based message authentication code, namely TMAC, is designed with Exclusive OR network coding. Based on TMAC and time synchronization technique, a joint detection is implemented to resist pollution attacks and replay attacks synchronously. The correctness of the detection service is proved. Finally, the performance evaluation shows that the detection scheme brings negligible extra-expense in communication bandwidth and computational complexity compared to MAC-based schemes, and consumes energy lowly compared to other joint detection schemes.

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.

Network coding has become a promising approach to improve the communication capability for WSN, which is vulnerable to malicious attacks. There are some solutions, including cryptographic and information-theory schemes, just can thwart data pollution attacks but are not able to detect replay attacks. In the paper, we present a lightweight timestamp-based message authentication code method, called as TMAC. Based on TMAC and the time synchronization technique, the proposed detection scheme can not only resist pollution attacks but also defend replay attacks simultaneously. Finally

A two-dimensional mesh-connected processor array is an extensively investigated architecture used in parallel processing. Massive studies have addressed the use of reconfiguration algorithms for the processor arrays with faults. However, the subarray generated by previous algorithms contains a large number of long interconnects, which in turn leads to more communication costs, capacitance and dynamic power dissipation. In this paper, we propose novel techniques, making use of the idea of network flow, to construct the high-performance subarray, which has the minimum number of long interconnects. First, we construct a network flow model according to the host array under a specific constraint. Second, we show that the reconfiguration problem of high-performance subarray can be optimally solved in polynomial time by using efficient minimum-cost flow algorithms. Finally, we prove that the geometric properties of the resulted subarray meet the system requirements. Simulations based on several random and clustered fault scenarios clearly reveal the advantage of the proposed technique for reducing the number of long interconnects. It is shown that, for a host array of size 512 × 512, the number of long interconnects in the subarray can be reduced by up to 70.05 percent for clustered faults and by up to 55.28 percent for random faults with density of 1 percent as compared to the-state-of-the-art.

Model checking is a mainstream method for formal verification of communicating sequential processes (CSP). Existing CSP Model Checkers are incapable of verifying multiple properties concurrently in one run of a model checker. In addition, the properties to be verified are described with CSP in most model checkers, which is good for refinement checking, but leads to limited description power and weak generality. In order to tackle the two problems, answer set programming(ASP), which is completely free of sequential dependencies, is used to construct a CSP bounded model checking framework, where the CSP model checking problem is turned into a computation problem of answer sets. CTL is extended with events to describe the properties to be verified. In addition, preprocessing technique of properties is proposed for the sake of reducing the expense spending on replicated verification of the same sub formulas. An ASP based description system is constructed for complete description of various CSP processes and automatic generation of parallel processes. We integrated all the methods into a CSP model checker - ACSPChecker. The feasibility and efficiency of our methods are illustrated by the experiments with a classic concurrency problem - dining philosophers problem.

Considering the execution path and cut operators of a Prolog program can improve the precision of program analysis. Known semantics for Prolog either makes use of limited amount of path information and hence leads to less precise analysis or is goal dependent and therefore not suitable for goal independent program analysis. This paper deals with the problems by proposing a goal-independent denotational semantics for Prolog with cut, from which we can compute the set of partially computed answers associated to each program point that are obtained in the execution of any goal. With existing abstraction techniques this semantics can be abstracted into a finitely computable semantics that can serve as a basis for goal-independent Prolog program analysis.