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Adar A. Kalir

dblp:88/2556 · also Adar Kalir · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis
scheduling		 0.212013
Optimal allocation of testers to products with a queue time restriction in sort testing · ICRA 2013
Electronic design automation › hardware verification and test
test scheduling		 0.212013
Optimal allocation of testers to products with a queue time restriction in sort testing · ICRA 2013
Electronic design automation › hardware verification and test › VLSI testing
wafer testing		 0.012013
Optimal allocation of testers to products with a queue time restriction in sort testing · ICRA 2013

Methods — techniques the papers use, named apart from their topics

queueing model · 0.2optimization · 0.2
YearPublicationVenuePosition
2013 Optimal allocation of testers to products with a queue time restriction in sort testing
abstract
The test of each wafer product in Sort (final IC testing) is done by allocating a tester and an appropriate Sort Interface Unit (SIU) to the product, to perform the test programs over the wafer. This allocation problem is a more complex allocation problem in the presence of a queue time restriction. In this paper, this problem is formulated and solved to determine the optimal allocation of testers and SIU's to wafer products over a planning horizon, such that overall WIP throughout the planning horizon is minimized. The optimal solution also comprehends restrictions on the amount of wafers that may be shipped to other testing sites and replenishment policies regarding new SIU's.
Adar A. Kalir
 ICRA1