Resistance-inductance-capacitance (RLC) network reduction refers to the formulation of small networks whose port behavior is similar to that of large RLC networks. Several network reduction algorithms have been developed in the last few years, but none exist for RLC networks which preserve passivity. The loss of passivity can be a serious problem because simulations of the reduced networks may encounter artificial oscillations or "time step too small" errors which render the simulations useless. This paper presents a set of well-conditioned transformations called "split congruence transformations" (SCTs) which can he used to preserve specified moments and resonances for RLC network reduction, and these transformations are proven to preserve passivity. Network reduction examples are provided to demonstrate the utility of SCTs.

None of the existing network reduction tools preserve passivityfor RLC networks. The loss of passivity can be a serious problembecause simulations of the reduced networks may encounter"time step too small" errors. This paper presents a set oftransformations called "Split Congruence Transformations"(SCT's) which can be used to accurately reduce a RLC networkwhile preserving passivity.

A novel technique is presented which employs pole analysis via congruence transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Pade approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. The error incurred by reducing the networks is shown to be bounded by values which are fully selectable by the user. Networks are represented by admittance matrices throughout the analysis, and this representation both simplifies interfacing the reduced networks with circuit simulators and facilitates realization of the reduced networks using RC elements. A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm.

A novel technique is presented which employs Pole Analysis via Congruence Transformations (PACT) to reduce RC networks in a well-conditioned manner.Pole analysis is shown to be more efficient than Padé approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks.Networks are represented by admittance matrices throughout the analysis, and this representation simplifies interfacing the reduced networks with circuit simulators as well as facilitates realization of the reduced networks using RC elements.A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm.

An approach is presented for modeling board level, package-level, and MCM substrate-level interconnect circuitry based an measured time domain refectometry data. The time-domain scattering parameters of a multiport system are used to extract a SPICE netlist which uses standard elements to match the behavior of the device up to a user-specified cutoff frequency. Linear or nonlinear circuits may be connected to the model ports, and the entire circuit simulated in a standard circuit simulator. Two-port and four-port example microstrip circuits are characterized, and the simulation results are compared with measured data. Delay, reflection transmission, and crosstalk are accurately modeled in each case.

We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixedsignal circuits.Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation.The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits.The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular signal cross talk through the common chip substrate has become increasingly problematic. The paper demonstrates a new methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. RC substrate network models, which are generated via a triangular discretization method, are accurately approximated for subsequent analysis by an efficient reduction algorithm. This algorithm utilizes the well-conditioned Lanczos process to formulate Pade approximations of the network port admittance. Congruence transformations are employed to ensure stability, and to create reduced networks which are easily realizable with SPICE-compatible RC elements. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.

Despite their potential benefits, statistical design/optimization techniques are often not routinely used by industry because of prohibitive costs and/or lack of generality. To overcome these obstacles, we present a general approach to statistical design which is computationally inexpensive and applicable to an extensive spectrum of analog-digital circuits, unlike previous inexpensive methods which limit the user to specific technologies, standard device models, and/or purely digital designs. This general applicability and cost efficiency is maintained through four factors. First, an efficient screening algorithm minimizes the dimensionality of the input parameter space by identifying the important input parameters. Second, a general, accurate, parsimonious nonparametric regression model is formulated so that a wide range of behavior between input parameters and output performances can be mapped, not just those with a linear regression relationship. Third, this approach tightly couples with a compiler-methodology based simulator which sustains the achieved flexibility through its model independence. Finally, a waveform analysis capability completely automates the procedure. An industry ECL bandgap regulator circuit illustrates the benefits of this method.>

We present a modeling technique for assessing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Since the magnitude of the noise problem is a function of the relative proximity of noisy and sensitive devices, design aids are required which can incorporate the switching noise effects at the post-layout phase of design verification. In our approach, SPICE-compatible lumped element RC substrate macromodels are efficiently generated from the circuit layout using a geometric construct called the Voronoi tessellation. The new models retain the accuracy of previously reported models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing larger circuits. The node count reduction is realized by deriving a model topology which automatically adapts itself to the local densities of substrate features associated with the noise coupling. Our strategy has been verified using detailed 2-D device simulation, and successfully applied to some mixed-A/D circuit examples.

Based on the partitioned-charge-based modeling approach, a general nonquasi-static dynamic charge element is derived to simulate both transient behavior and high-frequency characteristics of a semiconductor diode. A new model parameter /spl tau/ is introduced to describe the dynamic charge redistribution time for a diode. By partitioning the total base charge into quasi-static (QS) and nonquasi-static (NQS) terms, a single-/spl tau/ (level 2) diode model is first derived. By further dividing the NQS charge, a double-/spl tau/ (level 3) diode model is proposed to describe different reverse recovery processes. In addition, a voltage-dependent equation is incorporated to the double-/spl tau/ model into account for the dynamic charge partitioning. We show that the SPICE diode (level 1) model is included by setting /spl tau/ to zero as a special case of the proposed models. The new diode model has been implemented in MISIM, a model independent SPICE-like simulation framework. Significant improvement in accuracy over the traditional SPICE diode model in both time and frequency domain has been demonstrated, while achieving the same or even better simulation speed and reliability.>

Article An efficient non-quasi-static diode model for circuit simulation Share on Authors: Andrew T. Yang View Profile , Yu Liu View Profile , Jack T. Yao View Profile , R. R. Daniels View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 720–725https://doi.org/10.1145/157485.165107Published:01 July 1993 1citation306DownloadsMetricsTotal Citations1Total Downloads306Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Despite their indisputable benefits, parametric yield prediction/optimization techniques are often not routinely used by industry because of prohibitive costs and/or lack of generality. To overcome these obstacles, we present a new statistical technology independent parametric yield approach which is computationally inexpensive and generally applicable, unlike previous inexpensive methods which limit the user to specific technologies, device models, or circuits. This general applicability and cost efficiency is maintained through four factors. First, this approach interfaces with a compiler-methodology based simulator which establishes complete model independence. Second, critical parameters are not predetermined; an efficient screening procedure minimizes the dimensionality of the input parameter space so as to formulate a parsimonious nonparametric regression model. Third, because of the flexibility of this nonparametric model, the capability exists to map any input parameters to an output performance, not just those with a linear relationship. Finally, a waveform analysis capability completely automates the approach, thereby enabling turn-key operation. An ECL bandgap regulator circuit illustrates the benefits of this approach.

A method for switch-level timing simulation of bipolar emitter-coupled-logic (ECL) circuits is presented. The approach is based on the development of a switch level model of the transistor and on the representation of the circuit by a switch-graph. The circuit is partitioned into subcircuits, and the symbolic logic expressions, which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions, are then generated. Timing information is computed using a new physical delay model based on device equations, transistor interconnection, input slew rate, and loading conditions. The delay model was derived on the basis of average branch current analysis and incorporates more than 15 delay-sensitive circuit and SPICE BJT model parameters. The use of a novel parametric correction scheme permits greater freedom to handle complex effects such as high-level injection, parasitic resistances, and interconnection delay. In addition, the dynamic fanout effects due to base leakage current are incorporated by a fanout collapsing technique.>

The approach discussed is based on the efficient integration of the analog simulator with an analytic digital macromodel via the mixed A/D circuit partitioning, error and timestep control, and latency checking schemes. While maintaining accuracy constraints at every timepoint, this approach efficiently decouples the digital processing completely from the iteration-based analog algorithms. The waveform information of the digital subcircuits is provided at each timepoint by an accurate digital macromodel, which is derived analytically from the technology files. Therefore, advanced CMOS technologies can be incorporated easily. The proposed technique has been integrated into MISIM, a flexible CAE system for mixed A/D verification and rapid technology characterization. Several mixed A/D benchmark circuits have been tested and the results show that MISIM provides accurate mixed A/D simulation capability with a speed advantage of up to three orders of magnitude over SPICE3.>

Article Modeling and simulation of high-frequency integrated circuits based on scattering parameters Share on Authors: A. T. Yang NSF Center for Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, FT-10, Seattle, WA NSF Center for Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, FT-10, Seattle, WAView Profile , C. H. Chan NSF Center for Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, FT-10, Seattle, WA NSF Center for Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, FT-10, Seattle, WAView Profile , J. T. Yao NSF Center for Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, FT-10, Seattle, WA NSF Center for Design of Analog-Digital Integrated Circuits, Dept. of Electrical Engineering, University of Washington, FT-10, Seattle, WAView Profile , R. R. Daniels Boeing Aerospace & Electronics, High-Tech Center, PO Box 3999, Seattle, WA Boeing Aerospace & Electronics, High-Tech Center, PO Box 3999, Seattle, WAView Profile , J. P. Harrang Boeing Aerospace & Electronics, High-Tech Center, PO Box 3999, Seattle, WA Boeing Aerospace & Electronics, High-Tech Center, PO Box 3999, Seattle, WAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 752–757https://doi.org/10.1145/127601.127764Online:01 June 1991Publication History 12citation408DownloadsMetricsTotal Citations12Total Downloads408Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The authors present an approach for the analytical timing model development of bipolar VLSI circuits. The approach is based on the development of the delay functions of three basic bipolar subcircuits. It is shown that accurate timing information for two high-speed digital circuit constructs, ECL (emitter coupled logic) and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The timing models have been shown to be accurate typically within 10% of SPICE's estimates with up to three orders of speedup for large-scale BJT (bipolar junction transistor) circuits.>

The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.>

The laborious task of implementing a new device model in a circuit simulator has long been recognized as a painful bottleneck to device modeling. In contrast to the conventional circuit simulators which employ a built-in model library approach, iSMILE generates and links all the necessary codes automatically from a minimal set of model descriptions contained in a user's model input file.

The authors discuss optical interconnects, with emphasis on computer-aided modeling and simulation of optoelectronic integrated circuits (OEIC). Results are presented on laser diodes driven by GaAs MODFET driver circuits, optical waveguides, photodetectors and MODFET amplifiers to drive digital GaAs circuits. The models have been verified using iSMILE a CAD tool for OEIC. The speed advantage of optical interconnects over the conventional metallic interconnects has been projected in terms of the routing distance and the fanout count. The optical interconnect is clearly superior for long distance and for high fanouts. For short distance and low fanouts, it can also become superior when very-low-power laser diodes and more efficient photodetectors become available.>