In this paper, a new look-up table (LUT) method is proposed to reduce the simulation time and the run time memory requirement for large logic and mixed signal simulations. In the proposed method, for the first time, circuit with multiple devices is replaced by one LUT model, called circuit LUT. The replacement results in significant reduction of the run time memory requirement. The replacement also reduces the number of interpolation steps to be performed at every Newton-Raphson iteration during the simulation that results in significant reduction of simulation time. With the proposed method, the simulation speed is improved by two times over the conventional LUT models developed for devices. In addition, 25% reduction in the run time memory requirement is also achieved by the proposed method.

This paper describes an online laboratory for a course on electronic devices and circuits aimed at complementing classroom teaching of undergraduate courses. The development is based on four levels of teaching, viz., lecture notes, interactive tutorials, simulation exercises, and performing a real experiment remotely. The current facility has been developed to support an undergraduate theory course, “Electronic Devices and Circuits” as a pre-laboratory session for a regular on-site laboratory. It can be also used as an alternative to a traditional laboratory especially for distance education programs, or for interdisciplinary first year courses not having lab component. The facility has also been developed as a teaching tool for classroom demonstrations.

This paper presents a novel table-based approach for efficient statistical analysis of Finfield effect transistor circuits. The proposed approach uses a new scheme for interpolation of look-up tables (LUTs) with respect to process parameters. The effect of various process parameters, viz., channel length, fin width, and effective oxide thickness is studied for three circuits: buffer chain, static random access memory cell, and high-gain low-voltage op-amp. Compared to mixed-mode (device-circuit) simulation, the proposed LUT-based approach is shown to be much faster, thus making it practically a feasible and attractive option for variability analysis especially for emerging technologies where compact models are not available for circuit simulation.

A novel table-based environment for automatic design and optimization of FinFET circuits is demonstrated. A new accurate look-up table (LUT) technique is implemented in a circuit simulator and integrated with particle swarm optimization algorithm for efficient circuit designs in novel devices. Op-amp circuits are designed and optimized to demonstrate the accuracy and usefulness of the proposed platform. Further, it is shown that the proposed design methodology can take into account variations in process, supply voltage, and temperature.

Transistor variability has emerged as one of the important constraints in Nano-CMOS circuit design. The ever decreasing device feature size with CMOS scaling, has resulted in an increasing uncertainty in predicting the exact device behaviour. The issue of variability needs to be addressed across the entire hierarchy of integrated circuits - optimization of process and device technology to yield minimal variability, robust circuit and system design architectures for variability aware design, and CAD tools to unify these two domains. The traditional variability modeling and CAD techniques address the problem in one of the two domains. We propose a unified framework to bridge the gap between technology CAD and design CAD. This framework enables one to directly relate the variation in circuit metrics such as speed, static power and dynamic power to the underlying semiconductor process parameters such as implant dose, annealing temperature etc. The proposed methodology is validated through rigorous simulations at the process, device and circuit level, incorporating various statistical techniques. A few examples will be presented to elaborate the significance of the proposed modeling methodology and its utility in the Nano CMOS design flow. In addition to being an important utility in the circuit design flow, the methodology will also help the foundries by providing a visibility on the impact of unit processes on the eventual circuit characteristics. This in turn can help in a systematic and optimized process monitoring in the foundries.

A new lookup-table (LUT) approach, based on normalization of the drain current with anID-VGtemplate, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.

A generalized methodology for modeling the effects of process variations on circuit delay performance is proposed by directly relating the variations in process parameters to variations in delay metric of a digital circuit. The 2-input nand gate is used as a library element for 65 nm gate length technology, whose delay is extensively characterized by mixed-mode simulations. This information is then used in a general-purpose circuit simulator SEQUEL, by incorporating appropriate templates for the nand gate library. A 4-bit times 4-bit Wallace tree multiplier circuit, consisting of about 300 2-input nand gates, is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized by an extensive Monte Carlo analysis. To extend this methodology for a generic technology library with a variety of library elements, modeling of nand gate delays by response surface methodology (RSM), in terms of process parameters, is carried out using design of experiments (DOE). A simple piecewise quadratic model, based on the least squares method (LSM), is proposed for one-parameter variation to address significant cubic effects observed in the delay response function. Then, a hybrid model for gate delays is generated by superimposing the interaction terms of DOE-RSM model upon the quadratic model of one-parameter variation to address the generalized case of simultaneous variations in multiple process parameters. The proposed methodology has been demonstrated for nand gate library with 266 gates, and the simplicity and generality of the approach make it equally applicable to a large library of cells for both statistical timing analysis and statistical circuit simulation at the gate level

It is argued that the vector resolution discretization scheme is not consistent with the velocity saturation model. As a result, the simulation results show dependence on grid orientation. A modification is then presented to overcome this difficulty. Simulation examples are discussed to clearly demonstrate the improvement obtained with the new scheme. Finally, some comments are made regarding the convergence behaviour of the new scheme.

A new discretization scheme for semiconductor device simulation on triangular grids is proposed. Simulation examples are presented to show that solutions obtained with the commonly used box discretization scheme differ significantly depending on whether or not the grid contains obtuse triangles. On the other hand, it is shown that the new scheme is relatively insensitive to the presence of obtuse triangles. The reasons for the inconsistent behavior of the box scheme are examined. Some comments are made regarding the numerical efficiency of the new scheme as compared to the box scheme.