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Kouichi Itoh

dblp:88/2863 · DBLP profile ↗
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19ranked-venue papers
7as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 17 · 7 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
7 papers
Hardware security and side channels · 72% Cryptographic primitives and cryptanalysis · 28%
Computer architecture, parallel and distributed computing, and storage systems
4 papers
Integrated circuit design · 51% Reconfigurable computing and FPGAs · 35% Hardware accelerators and domain-specific architectures · 12%

Topics — the 14 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › hardware security primitives
physical unclonable function
0.112011
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches · CHES 2011
Cryptographic primitives and cryptanalysis › public-key cryptography
elliptic curve cryptography
0.152003
Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA · CHES 2000
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201 · CHES 1999
A Practical Countermeasure against Address-Bit Differential Power Analysis · CHES 2003
Reconfigurable computing and FPGAs
block cipher implementation
0.112008
A Very Compact Hardware Implementation of the MISTY1 Block Cipher · CHES 2008
Integrated circuit design › digital circuit design
cryptographic hardware
0.112008
A Very Compact Hardware Implementation of the MISTY1 Block Cipher · CHES 2008
Hardware security and side channels
side-channel countermeasures
0.122003
A Practical Countermeasure against Address-Bit Differential Power Analysis · CHES 2003
DPA Countermeasures by Improving the Window Method · CHES 2002
Integrated circuit design
digital circuit design
0.012011
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches · CHES 2011
Hardware security and side channels › side-channel attack › power analysis
differential power analysis
0.012002
Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA · CHES 2002
Hardware security and side channels › side-channel attack
power analysis
0.012002
Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA · CHES 2002
Hardware security and side channels › side-channel countermeasures
power analysis countermeasure
0.012002
DPA Countermeasures by Improving the Window Method · CHES 2002
Hardware security and side channels
side-channel attack
0.012002
Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA · CHES 2002
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.012000
Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA · CHES 2000
Cryptographic primitives and cryptanalysis
block cipher
0.012008
A Very Compact Hardware Implementation of the MISTY1 Block Cipher · CHES 2008
Cryptographic primitives and cryptanalysis
public-key cryptography
0.011999
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201 · CHES 1999
Processor architecture and microarchitecture › special-purpose processor
digital signal processor
0.011999
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201 · CHES 1999

Methods — techniques the papers use, named apart from their topics

physical unclonable function · 0.2compact hardware implementation · 0.2
YearPublicationVenuePosition
2016 ASIC implementation of random number generators using SR latches and its evaluation
abstract
A true random number generator (TRNG) is proposed and evaluated by field-programmable gate arrays (FPGA) implementation that generates random numbers by exclusive-ORing (XORing) the outputs of many SR latches (Hata and Ichikawa, IEICE Trans. Inf. Syst. E95-D(2):426–436, 2012). This enables compact implementation and generates high-entropy random numbers. In this paper, we fabricate and evaluate 39 TRNGs using SR latches on 0.18 μ m ASICs. Random numbers are generated by XORing the outputs of 256 SR latches. Our TRNGs pass the SP800-90B health tests and the AIS20/31 statistical tests in changing temperatures (from −20 to 60 °C) and voltages (1.80 ± 0.15 V). We also perform an independent and identically distributed (IID) test and calculate min-entropy according to the SP800-90B. With these tests, we are able to confirm that our TRNGs are highly robust against environmental stress. The power consumption and circuit scale of our TRNGs are 0.27 mW and 1240.5 gates, respectively. Our TRNGs that use SR latches are small enough to be implemented in embedded devices.
Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, Tsutomu Matsumoto
EURASIP J. Inf. Secur.4
2013 Privacy-Preserving Distributed Decision Tree Learning with Boolean Class Attributes
abstract
This paper studies a privacy-preserving decision tree learning protocol (PPDT) for vertically partitioned datasets. In the vertically partitioned datasets, a single class (target) attribute are shared by both parities or carefully treated by either party in the existing studies. The proposed scheme allows both parties to have independent class attributes in secure way and to combine multiple class attributes in arbitrary boolean function, which gives parties a flexibility in data-mining. Our proposed PPDT protocol reduces the CPU intensive computation of logarithm by approximating with the piecewise linear function defined by light-weight fundamental operations of addition and constant-multiplication so that information gain for attribute can be evaluated in the secure function evaluation scheme. Using the UCI Machine Learning dataset and the synthesized dataset, the proposed protocol is evaluated in terms of the accuracy and the size of tree.
Hiroaki Kikuchi, Kouichi Itoh, Mebae Ushida, Hiroshi Tsuda, Yuji Yamaoka
AINA2
2013 Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches
Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
CARDIS4
2012 Guest Editorial Integrated Circuit and System Security
abstract
The Guest Editors' primary objective in organizing this Special Issue was to provide additional impetus for research in hardware security. Currently, the field is heavily dominated by testing, CAD, and IC researchers. They hope that researchers from other security fields will find the problems and the proposed solutions published here both interesting and important. Ten Special Issue papers are represented in this collection.
Miodrag Potkonjak, Ramesh Karri, Ingrid Verbauwhede, Kouichi Itoh
IEEE Trans. Inf. Forensics Secur.4
2011 Exponent Blinding Does Not Always Lift (Partial) Spa Resistance to Higher-Level Security
Werner Schindler, Kouichi Itoh
ACNS2
2011 Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Takao Ochiai, Masahiko Takenaka, Kouichi Itoh
CHES7
2010 A Very Compact Hardware Implementation of the KASUMI Block Cipher
Dai Yamamoto, Kouichi Itoh, Jun Yajima
WISTP2
2008 A Very Compact Hardware Implementation of the MISTY1 Block Cipher
Dai Yamamoto, Jun Yajima, Kouichi Itoh
CHES3
2008 Small Secret Key Attack on a Variant of RSA (Due to Takagi)
Kouichi Itoh, Noboru Kunihiro, Kaoru Kurosawa
CT-RSA1
2006 Improving the Randomized Initial Point Countermeasure Against DPA
Kouichi Itoh, Tetsuya Izu, Masahiko Takenaka
ACNS1
2006 A Fast RSA Implementation on Itanium 2 Processor
Kazuyoshi Furukawa, Masahiko Takenaka, Kouichi Itoh
ICICS3
2004 Efficient Countermeasures against Power Analysis for Elliptic Curve Cryptosystems
Kouichi Itoh, Tetsuya Izu, Masahiko Takenaka
CARDIS1
2003 A Practical Countermeasure against Address-Bit Differential Power Analysis
Kouichi Itoh, Tetsuya Izu, Masahiko Takenaka
CHES1
2002 Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA
Kouichi Itoh, Tetsuya Izu, Masahiko Takenaka
CHES1
2002 DPA Countermeasures by Improving the Window Method
Kouichi Itoh, Jun Yajima, Masahiko Takenaka, Naoya Torii
CHES1
2001 The Block Cipher SC2000
Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima, Naoya Torii, Hidema Tanaka
FSE5
2000 Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA
Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka
CHES3
1999 Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201
Kouichi Itoh, Masahiko Takenaka, Naoya Torii, Syouji Temma, Yasushi Kurihara
CHES1
1997 Automated Detection of Breast Tumors in Ultrasonic Image Using Fuzzy Reasoning
abstract
This paper proposes a novel method for the automated detection of breast tumors in three dimensional ultrasonic images using fuzzy reasoning. The algorithm consists of two stages of processing. In the first stage a three dimensional LoG (Laplace of Gaussian) filtering is employed to generate a membership function for the fuzzy inference. In the second stage, each voxel in the three dimensional image is classified as "tumor", "normal tissue" or "boundary" by fuzzy reasoning followed by the defuzzification using relaxation techniques. We apply the method to 10 cases of malignant and 10 cases of benign tumors. Both of the two types of extracted tumors agree well with the manually traced boundaries. Further we define a parameter for evaluation of the uneven complexity of the surface roughness for diagnosis of malignant and benign tumors. The results show a successful characterization.
Xianyong Cheng, Iwaki Akiyama, Kouichi Itoh, N. Taniguchi, M. Nakajima
ICIP (3)3