Article Evaluation of parts by mixed-level DC-connected components in logic simulation Share on Authors: Dah-Cherng Yuan View Profile , Lawrence T. Pillage View Profile , Joseph T. Rahmeh View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 367–372https://doi.org/10.1145/157485.164934Online:01 July 1993Publication History 1citation129DownloadsMetricsTotal Citations1Total Downloads129Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Long branch delay is a well-known problem in today's high performance superscalar and supetpipeline processor designs.A common technique used to alleviate this problem is to predict the direction of branches during the instruction fetch.Counter-based branch prediction, in particular, has been reported as an effective scheme for predicting the direction of branches.However, its accuracy is generally limited by branches whose future behavior is also dependent upon the history of other branches.To enhance branch prediction accuracy with a minimum increase in hardware COSLwe propose a correlation-based scheme and show how the prediction accuracy can be improved by incorporating information, not only from the history of a specific brsncb but also from the history of other branches.Specifically, we use the information provided by a proper subhistory of a branch to predict the outcome of that branch.The proper subhistory is selected based on the outcomes of the most recently executed M branches.The new scheme is evaluated using traces collected from running the SPEC benchmark suite on an IBM RISC System/6000 workstation.The results show that, as compared with the 2-bit counter-based prediction scheme, the correlation-based branch prediction achieves up to 11 ~0 additional accuracy at the extra hardware cost of one shift register.The results also show that the accuracy of the new scheme surpasses that of the counter-based branch predction at saturation.

Event controlled pipelines (micropipelines) have several advantages over clocked pipelines as they offer modularity and speed independence. The concept of micropipelines can be easily applied to any linear pipeline. In practice, most pipelines include feedback loops and, therefore, are not as easy to control as linear pipelines. A novel interlocking scheme to solve the control flow problem is proposed. As an application, the design of a self-timed rebound sorter is considered where interlocking schemes are required to ensure proper operation of the pipeline. Similar interlocking schemes can be used for other pipelines with feedback.>

Cost-effective and accurate fault simulation of very large digital designs on engineering workstations is proposed. The hierarchical approach reduces memory requirements drastically by storing the structure of common repeated subcircuits only once. The approach allows flexible multilevel simulation. The simulation algorithms are at the switch-level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The fault simulation algorithms have been implemented as a prototype that was used to determine the fault grade of a model of the Motorola 68000 microprocessor on SUN Microsystems workstations.>

The design of fault-tolerant hypercube multiprocessor architecture is discussed. The authors propose the detection and location of faulty processors concurrently with the actual execution of parallel applications on the hypercube using a novel scheme of algorithm-based error detection. System-level error detection mechanisms have been implemented for three parallel applications on a 16-processor Intel iPSC hypercube multiprocessor: matrix multiplication, Gaussian elimination, and fast Fourier transform. Schemes for other applications are under development. Extensive studies have been done of error coverage of the system-level error detection schemes in the presence of finite-precision arithmetic, which affects the system-level encodings. Two reconfiguration schemes are proposed that allow the authors to isolate and replace faulty processors with spare processors.>

This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information about the design such as the structure, regularity, functionality, and control signals in the generation process. New algorithms are proposed and have been implemented for combinational modules and bus structures. A significant speedup has been obtained for these modules of a commercially available chip.

A fault simulation algorithm based on the partitioning of faults into groups, with the group size equal to the number of bits in the host computer word, is presented. The fault effects of a particular group are evaluated using parallel fault simulation techniques and propagated using concurrent fault simulation techniques. The speed of the algorithm depends on the circuit and on the fault-grouping criterion. Three static grouping criteria are examined and compared in terms of speed and memory requirements. A dynamic regrouping technique is developed and is shown to improve the performance of static grouping.>

The design and implementation of a hierarchical switch-level simulator for complex digital circuits is discussed. The hierarchy is exploited to reduce the memory requirements of the simulation, thus allowing the simulation of circuits that are too large to simulate at the flat level. The algorithm used in the simulator operates directly on the hierarchical circuit description. Speedup is obtained through the use of high-level models. The simulator has been implemented on a SUN workstation and used to simulate a switch-level description of the Motorola 68000 microprocessor.>

This paper describes FAUST, an MOS fault simulator with timing information. FAUST simulates the effects of realistic physical failures on MOS circuits and uses a static concurrent fault-simulation technique to evaluate the fault-free circuit and all the faulty circuits in one pass. FAUST produces voltage waveforms as well as logic tables with delay information for the fault-free circuit and for each of the faulty circuits.

article TIDBITS: speedup via time-delay bit-slicing in ALU design for VLSI technology Share on Authors: Peter Y. T. Hsu Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile , Joseph T. Rahmeh Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile , Edward S. Davidson Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile , Jacob A. Abraham Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champalgn Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-ChampalgnView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 29–35https://doi.org/10.1145/327070.327121Online:01 June 1985Publication History 5citation474DownloadsMetricsTotal Citations5Total Downloads474Last 12 Months6Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access