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Salvador Coll

dblp:88/2959 · DBLP profile ↗
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16ranked-venue papers
5as first author
1since 2021 · last 2023
0000-0002-7795-7252ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 14 · 5 first-author · 1 since 2021Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Energy-efficient computing · 50% Interconnection networks and networks-on-chip · 36% High-performance computing · 9%

Topics — the 13 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › energy-efficient communication
power-aware routing
0.412019
POWAR: Power-Aware Routing in HPC Networks with On/Off Links · ACM Trans. Archit. Code Optim. 2019
Energy-efficient computing
power management
0.412019
POWAR: Power-Aware Routing in HPC Networks with On/Off Links · ACM Trans. Archit. Code Optim. 2019
High-performance computing
collective communication
0.122009
Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009
Scalable Hardware-Based Multicast Trees · SC 2003
Interconnection networks and networks-on-chip › multicast
hardware multicast
0.122009
Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009
Scalable Hardware-Based Multicast Trees · SC 2003
Interconnection networks and networks-on-chip
interconnection networks
0.112019
POWAR: Power-Aware Routing in HPC Networks with On/Off Links · ACM Trans. Archit. Code Optim. 2019
Interconnection networks and networks-on-chip › network topology › tree networks
fat-tree network
0.112009
Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009
Interconnection networks and networks-on-chip › routing algorithms
fault-tolerant routing
0.112009
Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009
Interconnection networks and networks-on-chip › routing algorithms
multicast routing
0.012003
Scalable Hardware-Based Multicast Trees · SC 2003
Interconnection networks and networks-on-chip
routing and switching
0.012003
Scalable Hardware-Based Multicast Trees · SC 2003
Cloud and datacenter computing › cluster resource management and scheduling
cluster resource management
0.012002
STORM: lightning-fast resource management · SC 2002
Cloud and datacenter computing
job scheduling
0.012002
STORM: lightning-fast resource management · SC 2002
Interconnection networks and networks-on-chip › high-speed networks
supercomputer interconnect
0.012009
Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks · IEEE Trans. Parallel Distributed Syst. 2009
Cloud and datacenter computing
resource management
0.012002
STORM: lightning-fast resource management · SC 2002

Methods — techniques the papers use, named apart from their topics

power-aware routing · 0.4simulation · 0.1formal verification · 0.1greedy algorithm · 0.0backtracking · 0.0low-level network features · 0.0
YearPublicationVenuePosition
2023 Energy efficient HPC network topologies with on/off links
abstract
Energy efficiency is a must in today HPC systems. To achieve this goal, a holistic design based on the use of power-aware components should be performed. One of the key components of an HPC system is the high-speed interconnect. In this paper, we compare and evaluate several design options for the interconnection network of an HPC system, including torus, fat-trees and dragonflies. State of the art low power modes are also used in the interconnection networks. The paper does not only consider energy efficiency at the interconnection network level but also at the system as a whole. The analysis is performed by using a simple yet realistic power model of the system. The model has been adjusted using actual power consumption values measured on a real system. Using this model, realistic multi-job trace-based workloads have been used, obtaining the execution time and energy consumed. The results are presented to ease choosing a system, depending on which parameter, performance or energy consumption, receives the most importance.
Francisco J. Andujar, Salvador Coll, Marina Alonso, Juan-Miguel Martinez-Rubio, Pedro López 0001, José L. Sánchez 0002, Francisco J. Alfaro
Future Gener. Comput. Syst.2
2019 Energy efficient torus networks with on/off links
Francisco J. Andujar, Salvador Coll, Marina Alonso, Juan-Miguel Martinez-Rubio, Pedro López 0001, José L. Sánchez 0002, Francisco J. Alfaro, Raúl Martínez
J. Parallel Distributed Comput.2
2019 POWAR: Power-Aware Routing in HPC Networks with On/Off Links
abstract
In order to save energy in HPC interconnection networks, one usual proposal is to switch idle links into a low-power mode after a certain time without any transmission, as IEEE Energy Efficient Ethernet standard proposes. Extending the low-power mode mechanism, we propose POW er- A ware R outing ( POWAR ), a simple power-aware routing and selection function for fat-tree and torus networks. POWAR adapts the amount of network links that can be used, taking into account the network load, and obtaining great energy savings in the network (55%--65%) and the entire system (9%--10%) with negligible performance overhead.
Francisco J. Andujar, Salvador Coll, Marina Alonso, Pedro López 0001, Juan-Miguel Martinez-Rubio
ACM Trans. Archit. Code Optim.2
2015 Power consumption management in fat-tree interconnection networks
Marina Alonso, Salvador Coll, Juan-Miguel Martinez-Rubio, Vicente Santonja, Pedro López 0001
Parallel Comput.2
2011 Practical Student Teaching through Integrated True, Virtual and Remote Laboratories
Antonio Martí Campoy, José Carlos Campelo, Juan José Serrano, Marina Alonso, Salvador Coll
CSEDU (1)5
2010 Power saving in regular interconnection networks
Marina Alonso, Salvador Coll, Juan-Miguel Martinez-Rubio, Vicente Santonja, Pedro López 0001, José Duato
Parallel Comput.2
2009 Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks
abstract
This article presents an efficient and scalable mechanism to overcome the limitations of collective communication in switched interconnection networks in the presence of faults. Considering that current trends in supercomputing are moving toward massively parallel computers, with many thousands of components, reliability becomes a challenge. In such scenario, fat-tree networks that provide hardware support for collective communication suffer from serious performance degradation due to the presence of, even, a single faulty node. This paper describes a new mechanism to provide high-performance collective communication in such situations. The feasibility of the proposed technique is formally demonstrated. We present the design of a new hardware-based routing algorithm for multicast, that is at the base of our proposal. The proposed mechanism is implemented and experimentally evaluated. Our experimental results show that hardware-based multicast trees provide an efficient and scalable solution for collective communication in fat-tree networks, significantly outperforming traditional solutions.
Salvador Coll, Francisco J. Mora, José Duato, Fabrizio Petrini
IEEE Trans. Parallel Distributed Syst.1
2007 Power-Aware Fat-Tree Networks Using On/Off Links
Marina Alonso, Salvador Coll, Vicente Santonja, Juan-Miguel Martinez-Rubio, Pedro López 0001, José Duato
HPCC2
2006 Dynamic power saving in fat-tree interconnection networks using on/off links
abstract
Current trends in high-performance parallel computers show that fat-tree interconnection networks are one of the most popular topologies. The particular characteristics of this topology, that provide multiple alternative paths for each source/destination pair, make it an excellent candidate for applying power consumption reduction techniques. Such techniques are being increasingly applied in computer systems and the interconnection network is not an exception, since its contribution to the system power budget is not negligible. In this paper, we present a mechanism that dynamically switches on and off network links as a function of traffic. The mechanism is designed to guarantee network connectivity, according to the underlying routing algorithm. In this way, the default routing algorithm can be used regardless of the power saving actions taken, thus simplifying router design. Our simulation results show that significant network power consumption reductions can be obtained at no cost. Latency remains the same although the number of operating network links is dynamically adjusted.
Marina Alonso, Salvador Coll, Juan-Miguel Martinez-Rubio, Vicente Santonja, Pedro López 0001, José Duato
IPDPS2
2003 Scalable Hardware-Based Multicast Trees
abstract
This paper presents an algorithm for implementing optimal hardware-based multicast trees, on networks that provide hardware support for collective communication. Although the proposed methodology can be generalized to a wide class of networks, we apply our methodology to the Quadrics network, a state-of-the-art network that provides hardware-based multicast communication. The proposed mechanism is intended to improve the performance of the collective communication patterns on the network, in those cases where the hardware support can not be directly used, for instance, due to some faulty nodes. This scheme provides significant reduction on multicast latencies compared to the original system primitives, which use multicast trees based on unicast communication. A backtracking algorithm to find the optimal solution to the problem is presented. In addition, a greedy algorithm is presented and shown to provide near optimal solutions. Finally, our experimental results show the good performance and scalability of the proposed multicast tree in comparison to the traditional unicast-based multicast trees. Our multicast mechanism doubles barrier synchronization and broadcasts performance when compared to the production-level MPI library.
Salvador Coll, José Duato, Fabrizio Petrini, Francisco J. Mora
SC1
2003 Using multirail networks in high-performance clusters
abstract
Abstract Using multiple independent networks (also known as rails) is an emerging technique which is being used to overcome bandwidth limitations and enhance fault tolerance of current high‐performance parallel computers. In this paper, we present and analyze various algorithms to allocate multiple communication rails, including static and dynamic allocation schemes. An analytical lower bound on the number of rails required for static rail allocation is shown. We also present an extensive experimental comparison of the behavior of various algorithms in terms of bandwidth and latency. We show that striping messages over multiple rails can substantially reduce network latency, depending on average message size, network load and allocation scheme. The methods compared include a static rail allocation, a basic round‐robin rail allocation, a local‐dynamic allocation based on local knowledge and a dynamic rail allocation that reserves both communication endpoints of a message before sending it. The last method is shown to perform better than the others at higher loads: up to 49% better than local‐knowledge allocation and 37% better than the round‐robin allocation. This allocation scheme also shows lower latency and it saturates at higher loads (for long enough messages). Most importantly, this proposed allocation scheme scales well with the number of rails and message size. In addition we propose a hybrid algorithm that combines the benefits of the local‐dynamic allocation for short messages with those of the dynamic algorithm for large messages. Copyright © 2003 John Wiley & Sons, Ltd.
Salvador Coll, Eitan Frachtenberg, Fabrizio Petrini, Adolfy Hoisie, Leonid Gurvits
Concurr. Comput. Pract. Exp.1
2002 Scalable Resource Management in High Performance Computers
abstract
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highly-available computers. Although many hardware solutions are available today, the largest challenge in making largescale clusters usable lies in the system software. In this paper we present STORM, a resource management tool designed to provide scalability, low overhead, and the flexibility necessary to efficiently support and analyze a wide range of job-scheduling algorithms. STORM achieves these feats by using a small set of primitive mechanisms that are common in modern high-performance interconnects. The architecture of STORM is based on three main technical innovations. First, a part of the scheduler runs in the thread processor located on the network interface. Second, we use hardware collectives that are highly scalable both for implementing control heartbeats and to distribute the binary of a parallel job in near-constant time. Third, we use an I/O bypass protocol that allows fast data movements front the file system to the communication buffers in the network interface and vice versa. The experimental results show that STORM can launch a job with a binary of 12 MB on a 64-processor, 32-node cluster in less than 250 ms. This paper provides expert. mental and analytical evidence that these results scale to a much larger number of nodes. To the best of our knowledge, STORM significantly outperforms existing production schedulers in launching jobs, performing resource management tasks, and gang-scheduling tasks.
Eitan Frachtenberg, Fabrizio Petrini, Juan Fernández Peinador, Salvador Coll
CLUSTER4
2002 STORM: lightning-fast resource management
abstract
Although workstation clusters are a common platform for high-performance computing (HPC), they remain more difficult to manage than sequential systems or even symmetric multiprocessors. Furthermore, as cluster sizes increase, the quality of the resource-management subsystem — essentially, all of the code that runs on a cluster other than the applications — increasingly impacts application efficiency. In this paper, we present STORM, a resource-management framework designed for scalability and performance. The key innovation behind STORM is a software architecture that enables resource management to exploit low-level network features. As a result of this HPC-application-like design, STORM is orders of magnitude faster than the best reported results in the literature on two sample resource-management functions: job launching and process scheduling.
Eitan Frachtenberg, Fabrizio Petrini, Juan Fernández Peinador, Scott Pakin, Salvador Coll
SC5
2001 Using Multirail Networks in High-Performance Clusters
abstract
Using multiple independent networks (also known as rails) is an emerging technique to overcome bandwidth limitations and enhance fault tolerance of current high-performance clusters. We present an extensive experimental comparison of the behavior of various allocation schemes in terms of bandwidth and latency. We show that striping messages over multiple rails can substantially reduce network latency, depending on average message size, network load, and allocation scheme. The compared methods include a basic round-robin rail allocation, a local-dynamic allocation based on local knowledge, and a dynamic rail allocation that reserves both communication endpoints of a message before sending it. The last method is shown to perform better than the others at higher loads: up to 49% better than local-knowledge allocation and 37% better than the round-robin allocation. This allocation scheme also shows lower latency and it saturates on higher loads (for messages large enough). Most importantly, this proposed allocation scheme scales well with the number of rails and message sizes. In addition we propose a hybrid algorithm that combines the benefits of the local-dynamic for short messages with those of the dynamic algorithm for large messages.
Salvador Coll, Eitan Frachtenberg, Fabrizio Petrini, Adolfy Hoisie, Leonid Gurvits
CLUSTER1
2001 A First Implementation of In-Transit Buffers on Myrinet GM Software
abstract
Clusters of workstations (COWs) are becoming increasingly popular as a cost-effective alternative to parallel computers. In these systems, the interconnection network connects hosts using irregular topologies, providing the wiring flexibility, scalability, and incremental expansion capability required in this environment. Myrinet is the most popular network used to build COWs. It uses source routing with the up*/down * routing algorithm. In previous papers we proposed the In-Transit Buffer (ITB) mechanism that improves network performance by allowing minimal routing, balancing network traffic, and reducing network contention. The mechanism is based on ejecting packets at some intermediate hosts and later re-injecting them into the network. Moreover, the ITB mechanism does not require additional hardware as it can be implemented on the software running at Myrinet network adapters. In this paper, we present a first implementation of the ITB mechanism on Myrinet GM software. We show the changes required in packet format and the modifications performed in the Myrinet Control Program (MCP). In addition, both the overhead introduced by the new code and the cost of extracting and re-injecting packets are measured. Results show that, even for this simple implementation, code overhead is only about 125 ns per packet and the message latency increase for messages that use the ITB mechanism is around 1.3 s per ITB. This is the first attempt to implement this mechanism, showing that a real implementation of ITBs is feasible on Myrinet COWs, and the associated overhead does not restrict the potential benefits of this mechanism. 1.
Salvador Coll, José Flich, Manuel P. Malumbres, Pedro López 0001, José Duato, Francisco J. Mora
IPDPS1
2001 Hardware- and Software-Based Collective Communication on the Quadrics Network
abstract
The efficient implementation of collective communication patterns in a parallel machine is a challenging design effort, that requires the solution of many problems. In this paper we present an in-depth description of how the Quadrics network supports both hardware- and software-based collectives. We describe the main features of the two building blocks of this network, a network interface that can perform zero-copy user-level communication and a wormhole routing switch. We also focus our attention on the routing and flow control algorithms, deadlock avoidance and on how the processing nodes are integrated in a global, virtual shared memory. Experimental results conducted on 64-node AlphaServer cluster indicate that the time to complete the hardware-based barrier synchronization on the whole network is as low as 6 /spl mu/s, with very good scalability. Good latency and scalability are also achieved with the software-based synchronization, which takes about 15 /spl mu/s. With the broadcast, similar performance is achieved by the hardware- and software-based implementations, which can deliver messages of up to 256 bytes in 13 /spl mu/s and can get a sustained asymptotic bandwidth of 288 Mbytes/sec on all the nodes. The hardware-based barrier is almost insensitive to the network congestion, with 93% of the synchronizations taking less than 20 /spl mu/s when the network is flooded with a background traffic of unicast messages. On the other hand, the software-based implementation suffers from a significant performance degradation. With high load the hardware broadcast maintains a reasonably good latency, delivering messages up to 2KB in 200 /spl mu/s, while the software broadcast suffers from slightly higher latencies inherited from the synchronization mechanism. Both broadcast algorithms experience a significative performance degradation of the sustained bandwidth with large messages.
Fabrizio Petrini, Salvador Coll, Eitan Frachtenberg, Adolfy Hoisie
NCA2