Multiple-valued logic, in which the number of discrete logic levels is not confined to two, has been the subject of much research over many years. The practical objective of this work has been to increase the information content of the digital signals in a system to a higher value than that provided by binary operation. In this tutorial/survey paper we will review the historical developments in this field, both in circuit realizations and in methods of handling multiple-valued design data, and consider the present state-of-the-art and future expectations.

This paper describes the design of a new functional-cell gate-array with inherently high routability, and its automated customization software which achieves 100 percent first-time routing. Emphasis is placed upon the considerations which influence the selection of a functional array primitive. A highly structured interconnection architecture will be described, which employs interdigitating cell terminals in a polycell-like wiring channel topology to simplify the routing procedure for the array. The detailed structure and operation of an automatic customization software package is discussed. This package, developed specially for the array, utilizes the structured topology to achieve track densities which are comparable with those produced by state-of-the-art algorithms. This array has been fabricated, in a CMOS technology, as a test-vehicle for both the unusual topology and the unique functional cells. Throughout the study, emphasis has been placed on achieving a coherent strategy for producing efficiently routed gate-arrays with the minimum of sophisticated design tools. Examples will be cited to show that this methodology is economical both in the rapidity with which finished designs may be produced, and in its utilization of silicon-area.

This paper surveys the six possible variants of the basic universal-logic-module, ULM.2, and considers possible circuit realizations for each. A comparison of these variants in terms of circuit complexity, propagation delay, and total number of input/output connections is pursued, and detailed statistics generated to compare with previously published optimum data using conventional NAND and NOR gates.

Suarez, Chang, and Adam have recently disclosed an input-programmable logic configuration, with four input terminals to provide the specified range of function capability. Here we contrast the disclosure with an alternative line of universal logic element research, and indicate that three input terminals only are required in this alternative approach.

Previous developments by Winn (1975) on the design of single-output threshold-logic gates using Boolean product-of-sum expansions have been extended to the consideration of multioutput threshold-logic gates, by searching for optimum factorising of Winn functions to provide common terms for dissimilar threshold outputs. It has been found that such searches do not yield good results, but the combination of Winn plus parity functions is more viable. A need for more powerful digital synthesis techniques to handle multioutput design, with the ability to choose the number of logic levels per realisation, is found to be desirable for this and all other multioutput design problems.

A new mathematically based method of synthesis for combinational digital networks is presented, based upon the recognition of symmetry patterns in the functions being synthesized. The design procedure is structured such that at each stage of the synthesis a relevant gate assembly is indicated, which leaves a simplified "remainder" function to be synthesized at the next stage of the realization. This decomposition procedure optimally uses gates with a fan in of two, but post-synthesis reconfiguration for amalgamation into larger fan-in gates is available.

This paper surveys and brings together separate existing information from the field of (a) threshold logic synthesis, and (b) general binary synthesis using Rademacher-Walsh coefficients. The correlation between the Chow parameters widely used in the former and the latter Rademacher-Walsh coefficients is pursued. With a better understanding of the common features of both fields, inspiration towards further profitable developments may be hastened.