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Marco Mastrapasqua

dblp:88/367 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Electronic design automation · 44%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor device modeling
compact modeling
0.012000
Generation of equivalent circuits from physics-based devicesimulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation › technology computer-aided design
device simulation
0.012000
Generation of equivalent circuits from physics-based devicesimulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000

Methods — techniques the papers use, named apart from their topics

small-signal dc simulation · 0.0functional region partitioning · 0.0
YearPublicationVenuePosition
2000 Generation of equivalent circuits from physics-based devicesimulation
abstract
A novel technique for the numerical extraction of equivalent circuits from physics-based device simulation is presented. The method is based on the partitioning of the device into functional regions, each corresponding to a circuit block. All the circuit elements have a clear physical interpretation. Element values are directly obtained from small-signal dc device simulation. The method generates equivalent circuits of a complexity similar to the traditional approach, with model generation times comparable with those of black-box and physics-based device models. Applications to one-dimensional pn junctions and bipolar transistors are presented, discussing the extraction algorithm in detail.
Andrea Pacelli, Marco Mastrapasqua, Serge Luryi
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2