An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown.

Recent advances in the packaging technology of microelectronics have changed the design rules for printed wiring boards (PWB's) such that the number of wiring tracks between adjacent pins of an ordinary dual in line package (DIP) is allowed to be two or more, and the number of signal layers to be laminated is often required to be four or more. When the packaging density or scale of a PWB augments to such an extent, conventional routing schemes are confronted with various difficulties.

High-density packaging is one of the most urgent requirements in the design of digital systems. In the assembly of such systems, printed wiring boards (PWB's) are used very often to provide the necessary interconnection among circuit modules. Thus, methods to raise wirability of routers are continually under investigation.