Out-of-distribution (OOD) detectors can act as safety monitors in embedded cyber-physical systems by identifying samples outside a machine learning model’s training distribution to prevent potentially unsafe actions. However, OOD detectors are often implemented using deep neural networks, which makes it difficult to meet real-time deadlines on embedded systems with memory and power constraints. We consider the class of variational autoencoder (VAE) based OOD detectors where OOD detection is performed in latent space, and apply quantization, pruning, and knowledge distillation. These techniques have been explored for other deep models, but no work has considered their combined effect on latent space OOD detection. While these techniques increase the VAE’s test loss, this does not correspond to a proportional decrease in OOD detection performance and we leverage this to develop lean OOD detectors capable of real-time inference on embedded CPUs and GPUs. We propose a design methodology that combines all three compression techniques and yields a significant decrease in memory and execution time while maintaining AUROC for a given OOD detector. We demonstrate this methodology with two existing OOD detectors on a Jetson Nano and reduce GPU and CPU inference time by 20% and 28% respectively while keeping AUROC within 5% of the baseline.

Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as "Virtual SRAM Fab", for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32-22nm technology nodes.

With technology scaling, process constraints and imperfections result in significant variation of post-Si performance and stability of SRAM from designed/target pre-Si parameters. Modification/ re-optimization of SRAM cell and/or tuning of process parameters to meet target performance and stability are limited by area constraints and involve several technology ramp-up cycles. For reducing access failures, if process is not fine tuned, memory access clock cycle period may need to be increased thereby compromising performance. We propose a design methodology to meet the target performance and reduce access failures by tuning the SRAM array peripherals instead of tuning the SRAM cell and process parameters. Proposed design methodology is supported by numerical framework and validated by simulation results on 45nm PDSOI technology. We further show that our methodology does not impact the READ stability of a cell.

This article presents a holistic hybrid design methodology for low-power, low-cost, testable digital designs using low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). An alternate scaling rule under low thermal budget (due to flexible substrate) is developed to improve the performance of TFTs in the presence of process variation. We demonstrate that LTPS TFTs can be further optimized for ultralow-power subthreshold operation with performances comparable to contemporary single-crystal silicon-on-insulator (c-Si SOI) devices after process optimization. The optimized LTPS TFTs with high current drivability and less variability can comprise a promising low-cost option to augment Si CMOS technology, opening up a plethora of new hybrid 3D applications. We illustrate one such application: IC testing. Testing of complex VLSI systems is a prime concern due to design cost of DFT circuits, area/delay overheads, and poor test confidence. To harness the benefits of TFT technology, a novel low-power, process-tolerant, generic, and reconfigurable test structure designed using LTPS TFTs is proposed to reduce the test cost, as well as to improve diagnosability and verifiability, of complex VLSI systems. Due to proper optimization of TFT devices, the proposed test structure consumes low power but operates with reasonable performance. Furthermore, the test circuits do not consume any silicon area because they can be integrated on-chip using 3D technology. Since the test architecture is reconfigurable, this eliminates the need to redesign built-in-self-test (BIST) components that may vary from one processor generation to another. We have developed test structures using 200nm TFT devices and evaluated them on designs implemented in 130nm bulk CMOS. For circuit simulations, we have developed a SPICE-compatible model for TFT devices. The BIST components designed using the test structures operate at 0.8--4.3 GHz (compared to 8.2 GHz in bulk CMOS) with low power consumption. The enhanced scan cells partially implemented in TFT (3D hybrid design) consume ∼24% less power and ∼15--20% less area of Si die compared to conventional bulk-Si design (2D planar design), with minimal delay overhead.

We propose a design and optimization methodology for high performance and ultra low power digital applications on flexible substrate using low temperature polycrystalline silicon thin film transistor (LTPS TFT). We show that by using ultra-thin bodies and minimizing the mid-gap trap density by hydrogenation, LTPS TFTs (in 200 nm technology) can achieve higher performance than standard TFTs. We also demonstrate that it can be a promising candidate for both sub-threshold and super-threshold operation with performances comparable to contemporary bulk silicon. However, due to grain boundaries (GBs), there can be large intrinsic variations in such devices. Hence, there is a need for GB-tolerant design. Integration of proposed digital electronics in conjunction with conventional display application of LTPS TFTs on flexible substrates (system-on-panel) will open up plethora of new and interesting applications.

In this paper, we propose a methodology to solve leakage power self-consistently with temperature to predict thermal runaway. We target 28-nm-technology-node FinFET-based circuits as they are more prone to thermal runaway because of self-heating and less efficient heat dissipation compared to bulk metal-oxide-semiconductor field-effect transistors. We have generated thermal models for logic cells-inverter, NAND, and NOR-to self-consistently determine the temperature map of a circuit block. Our cell-level thermal models account for lateral heat flow (contribution of neighboring cells) along with vertical heat dissipation to the heat sink. We predict positive feedback between subthreshold leakage and temperature for all the cells in a given floor plan. Our proposed condition for thermal runaway shows the design tradeoff between the primary input (PI) activity of a circuit block, subthreshold leakage at the room temperature, and thermal resistance of the package. We show that, in FinFET circuits, thermal runaway can occur at the International Technology Roadmap for Semiconductors-specified subthreshold leakage (of 150 for high performance) for a nominal PI activity of 0.5 and typical package thermal resistance. In addition, we show that the maximum temperature rise in an integrated circuit is limited by package limitations.

With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. With the advent of FinFET technologies, cooling of a circuit is becoming a bigger challenge because of the thick buried oxide inhibiting the heat flow to the heat sink and confined ultra-thin channel increasing the thermal resistivity. In this work, we propose compact thermal models to predict the temperature rise in FinFET structures. We develop cell-level compact thermal models for standard INV, NAND and NOR gates accounting for the heat transfer across the six faces of a cell. Temperature maps of benchmark circuits exhibit close correspondence with dynamic power maps because of confined regions of heat generation separated by low thermal conductivity material. It is illustrated that temperature-aware timing analysis is imperative, because of high inter-cell temperature gradient. Accurate prediction of temperature in the early phase of design cycle gives valuable estimation of power/performance/reliability of a circuit block and guides in the design of more robust circuits.

We present a novel application for carbon nanotube devices, implementing a high density 3-D capacitor, which can be useful for decoupling applications to reduce supply voltage variations. The capacitor consists of staggered layers of interleaved carbon nanotubes, alternately connected to anode and cathode contacts. The device can realize a capacitance/area, significantly larger than the ITRS's projected requirements for year 2018. The capacitance per unit area can exceed 1pF/μm2, with a quality factor greater than 100 at 1GHz.

In this paper, we propose a general Circuit-aware Device Design methodology, which can improve the overall circuit design by taking advantages of the individual circuit characters during the device design phase. The proposed methodology analytically derives the optimal device in terms of the pre-specified circuit quality factor. We applied the proposed methodology to SRAM design and achieved significant reduction in standby leakage and access time (11% and 7%, respectively, for conventional 6T-SRAM). Also, we observed that the optimal devices selected depend considerably on the applied circuit techniques. We believe that the proposed Circuit-aware Device Design methodology will be useful in the sub-90nm technology, where different leakage components (subthreshold, gate, and junction tunneling) are comparable in magnitude. Also, in this work, we have presented a design automation framework for SRAM, which is conventionally custom designed and optimized.

In this work we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. We target 28n m FinFET based circuits as they are more prone to thermal runaway compared to bulk-MOSFETs. We generate thermal models for logic cells to self-consistently determine the temperature map of a circuit block. Our proposed condition for thermal runaway shows the design trade off between the primary input (PI) activity of a circuit block, sub-threshold leakage at the room temperature and the thermal resistance of the package. We show that in FinFET circuits, thermal runaway can occur at the ITRS specified sub-threshold leakage (150nA/μm, highperformance) for a nominal PI activity of 0.5 and typical package thermal resistance.

An analytical model is proposed to compute the fringe capacitance between two nonoverlapping interconnects in different layers using a conformal mapping technique. With this technique, electric field lines are geometrically approximated to separately model the different capacitive components. These components are finally combined to obtain the equivalent fringe capacitance. Using the aforementioned technique, a model was developed to compute the capacitances of typical interconnect geometries using technology-dependent parameters. The proposed model closely matches with FASTCAP results and significantly reduces the computational complexity and time in calculating the interconnect capacitances

Double-gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG devices, quasi-planar SOI FinFETs are easier to manufacture compared to planar double-gate devices. DG devices with independent gates (separate contacts to back and front gates) have recently been developed. DG devices with symmetric and asymmetric gates have also been demonstrated. Such device options have direct implications at the circuit level. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50nm circuits. Independent gate control can be used to merge parallel transistors in noncritical paths. This results in reduction in the effective switching capacitance and hence power dissipation. We show a variety of circuits in logic and memory that can benefit from independent gate operation of DG devices. As examples, we show the benefit of independent gate operation in circuits such as dynamic logic circuits, Schmitt triggers, sense amplifiers, and SRAM cells. In addition to independent gate option, we also investigate the usefulness of asymmetric devices and the impact of width quantization and process variations on circuit design.