Centralized and cloud computing-based network architectures are the promising tracks of future communication systems where a large scale compute power can be virtualized for various algorithms. These architectures rely on high-performance communication links between the base stations and the central computing systems. On the other hand, massive Multiple-Input Multiple-Output (MIMO) technology is a promising solution for base stations toward higher spectral efficiency. To reduce system complexity and energy consumption, 1-bit analog-to-digital converters (ADCs) are leveraged with the cost of lowering the signal quality. To recover the lost information, more sophisticated algorithms, like Joint Channel-and-Data (JCD) estimation, are required whose computation demand is a barrier toward practical implementation. In this paper, we suggest modifications to the current state-of-the-art JCD estimation algorithm to enhance its performance and ease the implementation costs. The modified algorithm delivers up to 4 dB higher symbol error rate in high SNR cases. This improvement is based on a new initialization strategy and an efficient exit condition with lower computation time. We implemented the proposed algorithm on a GPU accelerated system with higher throughput compared to the vanilla BiG-AMP algorithm suitable for software-defined radio systems. To the best of our knowledge, it is the first practical implementation of 1-bit JCD estimation for massive MIMO systems.

This paper focuses on an ef?cient approach of designing multi-static arrays for millimeter-wave imaging, based on the k-space or Fourier-spatial domain characteristic of imaging systems. Our goal is to decrease the redundancy of the data measured by each antenna, and to improve the resolution of the reconstructed image. The proposed technique is based on determining the role of each transmitter and receiver, in collecting the data from each voxel of the target in k-space domain and then rotating transmitters' beams to measure the desirable information. The effect of non-uniform redundant k-space domain frequency samples that act as an undesirable ?lter, is compensated using a modi?ed SAR back-projection algorithm. Experimental and simulation results are presented and compared with that of a sparse multi-static array with the same number of transmitters and receivers. Our simulations and measurements show signi?cant improvement in terms of overall quality and edge preservation in the reconstructed images. Also, the obtained results demonstrate that using the proposed structure and algorithm, the average improvement in peak-signalto-noise ratio (PSNR), structural similarity index measure (SSIM) and digital image correlation (DIC) metrics of 3.03 dB, 0.22 and 0.173, are achieved, respectively.

One of the solutions proposed to reduce system cost and power consumption in massive multiple-input multiple-output (MIMO) systems is the use of extremely low-resolution data converters in radio-frequency (RF) chains. The resulting severe signal distortion calls for more sophisticated data detection algorithms. The near Maximum-Likelihood (ML) detection schemes proposed so far, either exhibit numerical instability issues at high SNRs or suffer from prohibitively high computational complexity. In this paper, we propose a modified near-ML detection algorithm for the one-bit quantized case that eliminates the numerical issues with the lowest complexity among similar algorithms. We also present a low-complexity VLSI architecture for the proposed algorithm. Finally, we demonstrate the FPGA implementation results of the proposed architecture and show that its complexity is similar to that of linear detectors, while significantly outperforms them from the symbol error rate (SER) performance perspective.

In this paper, a new approach toward material detection and classification, based on the spectral analysis of millimeter-wave images, using machine learning technique is proposed. The focus of this paper is to detect concealed dangerous materials. It is shown that by using adequate number of training data captured from different materials of interest, the trained machine could detect concealed dangerous materials with an acceptable accuracy. The training phase is performed with materials of varying thickness, shape, background, covering layers and distance. The training data is collected with laboratory experiments in the frequency range of 27-31 GHz with 51 frequency samples. The results show more than 92 percent accuracy in differentiating various materials based on the true-alarm-rate (TAR) metric.

In this study, a thorough analysis of image reconstruction in an active millimetre‐wave (MMW) cylindrical imaging system is performed. To improve the system's performance in terms of the total cost as well as the coupling effect, sparse multi‐static arrays are desired. Nevertheless, the existing reconstruction methods fail to operate in sparse multi‐static antenna‐array systems. Therefore, to address these shortcomings, in this study, at first, the existing MMW mono‐static cylindrical image reconstruction methods are modified in both single‐frequency and wideband reconstruction platforms. Moreover, in order to further improve the image quality and the system cost, a sparse multi‐static one‐dimensional antenna array has been proposed. To use this sparse array in the cylindrical MMW imaging system, a novel multi‐static cylindrical image reconstruction method is also proposed. The performances of the proposed reconstruction methods for both mono‐static and sparse multi‐static cylindrical imaging structures are validated through numerical simulations. Through the obtained results, 83% reduction in antenna array cost along with a 25 dB decrease in coupling effect is achieved at the cost of a minor reduction in the reconstructed image quality.

5-th generation mobile networks aim the peak data rates in excess of few Gbs, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this paper, a new property of the QPP interleaver, called the correlated shifting property, is theoretically proved, leading to a fully scalable interleaver and a low-complexity address generator for an arbitrary order of parallelism. The proposed interleaver reduces the required addresses in half. Moreover, the scalability of the proposed interleaver proves up to 51% lower power consumption compared to the best reported interleaver to-date.

This paper presents a novel approach based on pulse transit time (PTT) for the estimation of blood pressure (BP). In order to achieve this goal, a data acquisition hardware is designed for high-resolution sampling of phonocardiogram (PCG) and photoplethysmogram (PPG). These two signals can derive PTT values. Meanwhile, a force-sensing resistor (FSR) is placed under the cuff of the BP reference device to mark the moments of measurements accurately via recording instantaneous cuff pressure. For deriving the PTT-BP models, a calibration procedure including a supervised physical exercise is conducted for each individual. The proposed method is evaluated on 24 subjects. The final results prove that using PCG for PTT measurement alongside the proposed models, the BP can be estimated reliably. Since the use of PCG requires a minimal low-cost hardware, the proposed method enables ubiquitous BP estimation in portable healthcare devices.

In this paper, a new method to achieve very small current reference levels on integrated circuits with immunity to temperature variations using peaking current source with MOSFETs operating in subthreshold region is proposed. By adding a source degeneration resistor to the conventional peaking current source architecture, a zero temperature coefficient current can be generated. The proposed low-power circuit operating in the weak inversion region is designed, simulated, and fabricated in a 0.18-μm standard CMOS process. Measurement results verify the circuit operation with about 5% variation over the span of −40° C to +100° C (industrial temperature grade). The supplied current is designed to be 1.5μΑ.

LDPC codes are deployed in many modern wired and wireless communication systems. While fully-parallel LDPC decoders are very efficient, they typically suffer from routing complexity. The Split-Row method effectively reduces this complexity with a minor performance loss. This paper shows the importance of symmetry in Split-Row architectures and proves that the implementation of Split-Row decoders based on new proposed smart column-permuted versions of parity check matrices leads to a better error performance as well as a more efficient hardware. Moreover, in order to achieve optimized column-permuted parity check matrices, a heuristic approach is proposed. This method is then generalized to support QC-LDPC codes. Applied to IEEE 802.3an (10GBASE-T Ethernet) and IEEE 802.11n (Wi-Fi) LDPC decoders, the new technique improves the error performance, while leading to almost 3× speed-up in the synthesis compile time and about 10% reduction in the critical path.

Long term evolution (LTE)-advanced aims the peak data rates in excess of 3 Gbps for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffers from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a Posteriori (MAP) cores in parallel, resulting in a large area overhead, a big drawback. The scaled Max-log MAP algorithm is a common approach to implement the MAP algorithm due to its efficient architecture with its acceptable performance. Although many works have been reported to reduce the area of the MAP unit, an efficient VLSI architecture with minimum silicon area is still missing. To address this challenge, in this paper, a novel method based on a novel form of computation is introduced, removing a single bit from computations of the max-log MAP algorithm compared to the conventional architectures. The proposed method can be applied to any max-log MAP architecture reported to-date.

Recently a few methods have been proposed in the literature for non-invasive cuff-less estimation of systolic and diastolic blood pressures. One of the most prominent methods is to use the Pulse Transit Time (PTT). Although it is proven that PTT has a strong correlation with the systolic and diastolic blood pressures, this relation is highly dependent to each individuals physiological properties. Therefore, it requires per person calibration for accurate and reliable blood pressure estimation from PTT, which is a big drawback. To alleviate this issue, in this paper, a novel method is proposed for accurate and reliable estimation of blood pressure that is calibration-free. This goal is accomplished by extraction of several physiological parameters from Photoplethysmography (PPG) signal as well as utilizing signal processing and machine learning algorithms. The results show that the accuracy of the proposed method achieves grade B for the estimation of the diastolic blood pressure and grade C for the estimation of the mean arterial pressure under the standard British Hypertension Society (BHS) protocol.

Split-Row technique is proved to be one of the most effective methods to reduce the routing complexity of fully-parallel LDPC decoders. This technique is based on the idea of splitting each check node processor to multiple smaller processors. This paper introduces a new method, to increase the power-efficiency of Split-Row LDPC decoders. The proposed method is called trust to the truthful check node (TTCN), enabling the decoder to only depend on a portion of check node processors at specific decoding iterations. This leads to an average reduction of 30%-40% in the check node dynamic power consumption. This is achieved by means of trust to a minority of check node processors and gating the others. In fact, a great side effect of the proposed method is also a slight improvement in the error performance.

A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, which allows for a high-accuracy compensation in a short interval. In the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the primary synchronization signal detection. In addition, we propose the sign-bit maximum-likelihood sequence detection algorithm for the secondary synchronization signal analysis. These methods result in 90% hardware reduction in the cell search compared with the state-of-the-art design. Moreover, possible structures for the frequency tracking in LTE are investigated leading to an experimental comparison, used to choose the best hardware-efficient structure. The proposed architecture is fabricated in a 130-nm CMOS technology occupying 0.68 mm2of silicon area. At 25 °C and 1.2 V supply voltage, the fabricated chip consumes 34.4 mW at 42 MHz in the time domain and 34.6 mW at 188 MHz in the frequency domain. The fabricated and tested synchronizer core proves to have an outstanding performance for all defined communication modes in LTE.

This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW.

An efficient low-complexity VLSI architecture for timing synchronization of a real-time intensity modulation direct detection optical OFDM (IMDD-OOFDM) system is proposed, which results in a significant area reduction. This architecture calculates the correlation among cyclic prefix (CP) regions to estimate the beginning of the OFDM symbol. The proposed architecture utilizes only one functional unit for this purpose, while the throughput is devised for high data-rate optical OFDM systems. Synthesis results of this architecture proves an area saving of 31% compared to the previous work. Moreover, the performance of the correlation method is significantly improved due to a modification applied in the algorithm. Simulation results show that the proposed method is very promising for new optical OFDM systems where the number of subcarriers and CP length is usually lower than conventional wireless systems.

Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design requires no memory or QPP inverse to perform deinterleaving and has been fully implemented and tested both on a Virtex-6 FPGA as well as in a 0.18 um CMOS process.

Continuous and remote monitoring of vital health-related and physical activity signs of a patient is one of the most important technology-oriented applications to monitor the health-care of ill individuals. In this paper, an innovative framework for a wireless Body Area Network (BAN) system, based on the IEEE 802.15.6 standard, with three types of sensors is proposed and implemented. These include Electrocardiogram (ECG), Force Sensitive Resistor (FSR) and Gyroscope. The proposed design is a novel implementation of an embedded system for the real-time processing and analyzing of the ECG signal, gait phases, and detection of the respiration rate from the ECG signal, by means of small applicable sensors and wireless data communication. Gait analysis is essential for the precise ECG and respiration analysis according to the body posture. A new comprehensive high-speed six-state design is utilized to cover all walking habits. Moreover, the collected data is sent to an external device for further monitoring. The proposed framework is optimized for hardware implementation and targeted for low power applications. The optimized joint implementation of these health-related sensors makes the proposed design distinct from the previous work.

Monitoring the respiratory signal is crucial in many medical applications. Traditional methods for the respiration measurement are normally based on measuring the volume of air inhaled and exhaled by lungs (like spirometer) or oxygen saturation in blood. However, these methods have numerous challenges including their high cost and not being accessible in some cases. In this paper, an algorithm for deriving the respiratory signal from ECG signal is proposed, which is based on other proposed algotithms. This algorithm uses the cubic spline interpolation (CSI) of R-waves in ECG to derive the respiratory signal. The CSI algorithm is made efficient with respect to ECG features in order to reduce the latency and the complexity of calculations. In addition, a hardware architecture for real-time and low-power processing is implemented. This architecture is synthesized using 180nm process and consumes 817μW. The FPGA tests are also performed on Xilinx Virtex-6 platform.

A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of the search tree on demand, rather than exhaustively, as well as a new distributed sorting scheme to keep track of the best candidates at each search phase. Its support of unbounded infinite lattice decoding distinguishes the present method from previous K-Best strategies and also allows its complexity to scale sublinearly with the modulation order. Since the expansion and sorting cores are data-driven, the architecture is well suited for a pipelined parallel VLSI implementation. The proposed algorithm is used to fabricate a 4×4, 64-QAM complex multiple-input-multiple-output detector in a 0.13-μm CMOS technology, achieving a clock rate of 417 MHz with the core area of 340 kgates. The chip test results prove that the fabricated design can sustain a throughput of 1 Gb/s with energy efficiency of 110 pJ/bit, the best numbers reported to date.

This paper presents the first silicon-proven implementation of a lattice reduction (LR) algorithm, which achieves maximum likelihood diversity. The implementation is based on a novel hardware-optimized due to the Lenstra, Lenstra, and Lovász (LLL) algorithm, which significantly reduces its complexity by replacing all the computationally intensive LLL operations (multiplication, division, and square root) with low-complexity additions and comparisons. The proposed VLSI design utilizes a pipelined architecture that produces an LR-reduced matrix set every 40 cycles, which is a 60% reduction compared to current state-of-the-art LR field-programmable gate array implementations. The 0.13-μm CMOS LR core presented in this paper achieves a clock rate of 352 MHz, and thus is capable of sustaining a throughput of 880 Mb/s for 64-QAM multiple-input-multiple-output detection with superior performance while dissipating 59.4 mW at 1.32 V supply.

A novel low-complexity detection scheme is proposed for the multiple-input multiple-output (MIMO) single-carrier frequency division-multiple access (SC-FDMA) systems, which is suitable for ASIC implementations. The proposed detection scheme makes an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) frequency domain equalizer (FDE) detector and finds symbols with higher error probability among them and browse more candidates for them in the constellation to improve their initial estimate. Based on this approach, architecture is introduced that achieves superior bit error rate (BER) performance compared to the conventional MMSE FDE. The performance of the proposed design is close to the existing maximum likelihood-post detection processing (ML-PDP) scheme, while achieving a significantly lower complexity , i.e., 450× less Euclidean distance (ED) calculations in 16-QAM. The ASIC implementation of the proposed architecture, the first ASIC for SC-FDMA detectors to-date, achieves a 3× higher throughput than the best design reported to-date.

This paper introduces a novel scalable pipelined VLSI architecture for a 4 × 4 64-QAM hard-output multiple-input-multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 μm CMOS, it occupies 0.95 mm2core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no BER performance loss. It achieves an SNR-independent throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and long term evolution (LTE) systems. The measurements confirm that this design consumes 3.0 × less energy/bit and operates at a significantly higher throughput compared to the best previously published design.

Lattice Reduction (LR) has been proposed as a method to enhance the performance of MIMO detectors such as ZF, MMSE and V-BLAST. Until recently, the application of LR to the superior K-Best tree-search detection algorithm was not practical due to the significant increase in complexity of K-Best as a result of the distortion of tree symmetry caused by LR. However, in our recently published work we developed an innovative K-Best algorithm to accommodate tree-asymmetry with no additional complexity. In this work, we build on this result and perform a detailed analysis of the effect of various LR algorithms on the performance of LR-aided K-Best. We show that LLL and Seysen provide equivalent performance enhancement, however, LLL displays a lower computational complexity and thus is more suitable for LR-aided K-Best. In this work we also show that the application of LR to K-Best allows a large reduction of the K value while maintaining its near-ML performance. For 64-QAM MIMO detection, this leads to about 70% reduction in the complexity of the K-Best detector.

This paper presents a VLSI architecture of a novel soft-output K-Best MIMO detector. The proposed detector attains low computational complexity using three improvement ideas: relevant discarded paths selection, last stage on-demand expansion, and relaxed LLR computation. A deeply pipelined architecture for a soft-output MIMO detector is implemented for a 4×4 64-QAM MIMO system realizing a peak throughput of 655Mbps, while consuming 174K gates and 195mW in 0.13um CMOS. Synthesis results in 65nm CMOS show the potential to support a sustained throughput up to 2Gbps achieving the data rates envisioned by emerging IEEE 802.16m and LTE-Advanced wireless standards.

This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity additions and comparisons. The VLSI implementation uses a pipelined architecture that produces an LR-reduced matrix every 40 cycles, which is a 60% reduction compared to current implementations. The proposed design was synthesized in both 130μm and 65nm CMOS resulting in clock speeds of 332MHz and 833MHz, respectively. The 65nm result is a 4× improvement over the fastest LR implementation to date. The proposed LR implementation is able to sustain a throughput of 2Gbps, thus achieving the high data rates required by future standards such as IEEE 802.16m (WiMAX) and LTE-Advanced.

QR decomposition (QRD) is an essential signal processing task for many MIMO signal detection schemes. However, decomposition of complex MIMO channel matrices with large dimensions leads to high computational complexity, and hence results in either large core area or low throughput. Moreover, for mobile communication applications that involve fast-varying channels, it is required to perform QR decomposition with low processing latency. In this paper, we propose a hybrid QRD scheme that uses a combination of multi-dimensional Givens rotations, Householder transformations and the conventional two-dimensional (2D) Givens rotations to both reduce the overall computational complexity and achieve higher execution parallelism. To prove the effectiveness of the proposed QRD scheme, a novel pipelined architecture is presented that uses un-rolled pipelined CORDIC processors iteratively to maximize throughput and resource utilization, while minimizing the gate count. The architectures of the main data processing modules, namely the 2D, Householder 3D and 4D/2D configurable pipelined CORDIC processors, are also presented. Synthesis results for a 4times4 MIMO detector in 0.13 mum CMOS process indicate that this QRD design computes a 4times4 complex R matrix and four updated 4times1 complex symbol vectors every 40 cycles, at a clock frequency of 270 MHz and requires 36 K gates. The proposed design achieves the lowest processing time and the highest throughput reported to-date for the same framework.

In this paper, a practical pipelined K-best lattice decoder featuring efficient operation over infinite complex lattices is proposed. This feature is a key element that enables it to operate at a significantly lower complexity than currently reported schemes. The main innovation is a simple means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively or approximately, and also directly within the complex-domain framework. In addition, a new distributed sorting scheme is developed to keep track of the best candidates at each search phase; the combined expansion and sorting cores are able to find the K best candidates in just K clock cycles. Its support of unbounded infinite lattice decoding distinguishes our work from previous K-best strategies and also allows its complexity to scale sub-linearly with modulation order. Since the expansion and sorting cores cooperate on a data-driven basis, the architecture is well-suited for a pipelined parallel VLSI implementation of the proposed K-best lattice decoder. Comparative results demonstrating the promising performance, complexity and latency profiles of our proposal are provided in the context of the 4x4 MIMO detection problem.

An efficient lattice-reduction (LR) aided implementation of the K-best algorithm is proposed for the general infinite lattice detection problem, which is realized with about 80% less complexity than currently reported architectures. The saving in complexity is achieved by the introduction of an on-demand candidate generation scheme along with a distributed sorting scheme. The proposed scheme does not require any a priori knowledge of the candidate displacement as it expands the candidates using the Schnorr-Euchner method. It is scalable in terms of the number of transmit antennas and its complexity grows sub-linearly with the constellation order. The parallelism intrinsic to the algorithm makes it suitable for the pipelined VLSI implementation.

A scalable pipelined VLSI architecture for K-best lattice decoders featuring an efficient operation over infinite lattices is proposed. The proposed architecture operates at a significantly lower complexity than currently reported schemes. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in just K clock cycles. Its support of the unbounded lattice decoding distinguishes our work from previous K-best strategies. Since the expansion and sorting cores cooperate on a data-driven basis, the architecture is well-suited for a pipelined parallel VLSI implementation. The proposed architecture has the lowest latency reported to-date, fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distribute sorters, pipelined high-throughput implementation, and is scalable to higher number of antennas/constellation orders.

This paper presents a sequential Monte Carlo (SMC) framework in order to compensate for the nonlinear distortion caused by solid-state power amplifiers (SSPA) in M-QAM schemes. The performance of this new approach is shown for low and high-order constellation schemes for different values of input backoff (IBO). The results reveal that, in low-IBO regimes, the SMC method shows a significant improvement, relative to the conventional methods where the predistorter is used before the amplifier, especially for high order constellations. Moreover, the SMC method is shown to have more robust behavior to the constellation scaling. Finally, an adaptive sequential Monte Carlo receiver is proposed that adapts itself efficiently to variations in amplifier parameters.

A systolic VLSI architecture is developed for a sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The architecture exploits the parallelism intrinsic to the algorithm. The SMC receiver consists of the SMC core, weight calculator, and sampler. Hardware efficient architectures for each functional block are proposed. Detailed features of various mappings of the proposed VLSI architecture for the SMC core are studied. Performance analyzes at both the architecture level and system level, are also presented

Considering the wide range of applicability of particle filters, their VLSI implementation is of great importance. Resampling is the sequential part of the fully parallel particle filter. Therefore, parallel VLSI architectures for resampling is of particular interest. In this paper, we develop a parallel implementation of resampling. The novel feature of the proposed architecture is that the execution time of resampling becomes independent of the distributions of the weights. Despite the alternatives in the literature, our scheme achieves a very small execution time by pipelining the resampling and sampling steps. Moreover, it is scalable for high levels of parallelism, has lower memory usage, fixed routing time, and has close to ideal performance. Furthermore, it eliminates the need for a point-to-point network between processing elements and results in a simple central unit

In this paper, using the dynamic pricing platform, a novel framework for downlink resource allocation in heterogeneous cellular CDMA networks is proposed. For each user, we define a utility that is a function of channel status and delay condition of that individual user as well as network load status. The network utility is then defined as the summation of the users' achieved utilities. We solve downlink resource allocation problem through maximization of total network utility. This approach results in a suboptimal base-station assignment scheme which-unlike previous work-is network optimal instead of cell optimal. We then show that optimal base-station assignment is a multidimensional multiple-choice Knapsack problem (MMKP). Since MMKP is NP-Hard a polynomial-time suboptimal heuristic algorithm is then employed to develop an efficient base-station assignment.

In this paper, using the concept of capacity regions, an algorithm for joint rate allocation and routing scheme is proposed in order to maximize the total throughput of multihop cellular CDMA networks. The notion of infeasibility factor is defined and used to propose an adaptive scheme on top of the above algorithm to manage fundamental coverage-capacity tradeoff for the downlink. In fact, the output of our algorithm is the joint rate allocation, routing scheme and base station (relay) assignment which in conjunction with the proposed adaptive scheme leads to implementing the concept of cell breathing via allocating proper transmit powers to base stations and relays. We show that our optimization problem can be mapped to a multidimensional multichoice knapsack problem (MMKP). Since MMKP is NP-hard, a polynomial-time heuristic algorithm is then developed to solve our MMKP.