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Menghui Zheng

dblp:88/4399 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 38% Electronic design automation · 38% Integrated circuit design · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing
dynamic power reduction		 0.011996
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › physical design › cell layout
transistor reordering		 0.011996
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Integrated circuit design › digital circuit design
CMOS circuit design		 0.011996
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Integrated circuit design
digital circuit design		 0.011996
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996

Methods — techniques the papers use, named apart from their topics

signal probability analysis · 0.0circuit simulation · 0.0
YearPublicationVenuePosition
1996 Reducing power dissipation in CMOS circuits by signal probability based transistor reordering
abstract
This paper introduces novel transistor reordering schemes to reduce the expected or average dynamic power dissipation in CMOS circuits. The transistor reordering is based on the signal probability values at the inputs of the gates. The paper begins with a simple analytical model for the dynamic power dissipation in a static NAND gate. The model is used to derive an algorithm for transistor reordering which reduces dynamic power dissipation. A simulation technique for accurately measuring the power dissipation in NAND gates is also presented, along with the results of the reordering algorithm. A transistor reordering algorithm for CMOS complex gates is subsequently presented. Transistor reordering is found to be an effective way to reduce power dissipation in all of these circuits, with the reduction in dynamic power dissipation compared to the worst case configuration, being as high as 50% in some instances. The limited overhead associated with transistor reordering encourage its application as a low power design technique.
Razak Hossain, Menghui Zheng, Alexander Albicki
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1995 Low power and high speed multiplication design through mixed number representations
abstract
A low power multiplication algorithm and its VLSI architecture using a mixed number representation is proposed. The reduced switching activity and low power dissipation are achieved through the Sign-Magnitude (SM) notation for the multiplicand and through a novel design of the Redundant Binary (RB) adder and Booth decoder. The high speed operation is achieved through the Carry-Propagation-Free (CPF) accumulation of the Partial Products (PP) by using the RB notation. Analysis showed that the switching activity in the PP generation process can be reduced on average by 90%. Compared to the same type of multipliers, the proposed design dissipates much less power and is 18% faster on average.
Menghui Zheng, Alexander Albicki
 ICCD1
1994 Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering
abstract
In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results indicate that transistor reordering can significantly reduce the power dissipation in CMOS NAND gates.>
Razak Hossain, Menghui Zheng, Alexander Albicki
 ICCD2