Efficient data output from large size array structures (such as large size array processor, as may be encountered in single chip large size Artificial Retinas (AR)) is problematic. Wiring cost to connect separately any element of the array is unacceptable. I/O performance are low to access the inner part of the array as I/O are usually done from the border, then moved onto or from the whole structure. This paper describes a structure that implements efficient output of position information at minimal hardware cost. It gives the coordinates of an element of the array that is either in an active state or needs to signal itself. Some solutions have already been proposed, mainly to be able to monitor the activity of array of neurons in a VLSI circuit for perceptive systems. To our knowledge, the structure proposed improves both on compactness and speed over other known methods. Operating principle, structure schematics, simulation and performance issues are presented in this paper. It was first developed to provide high performance output of pixel coordinates, results from images processed in large size digital PARs (Programmable Artificial Retinas). These PARs are single chip optical sensors composed of an SIMD array processor with optical input: a tiny processor is embedded in each pixel of a CMOS image sensor.

We propose in this paper a new 3D fully parallel thinning algorithm that we believe to be the most concise due to its simple characterization. The algorithm is indeed completely defined by a set of five patterns, three removing conditions and two non-removing conditions. These patterns are designed from the two fundamental and compatible constraints usually expected in skeleta: (1) Topology preservation and (2) Medial surface. From these two constraints, the removing patterns terns (/spl alpha//sub 1/, /spl alpha//sub 2/ and /spl alpha//sub 3/) detect the non-local maxima, whereas the non-removing patterns (/spl beta//sub 1/ and /spl beta//sub 2/) prevent any topology change that the removing conditions could imply. We show that the three mentioned constraints are respected. The logical conciseness of our procedure, called MB-3D, makes it to our knowledge the easiest 3D thinning algorithm to implement. Some results are displayed, that illustrate the relevance of our approach.

The introduction of intelligence near each photosensitive element in focal plane arrays (FPA) leads to sensory devices-called artificial retinas-which may no longer output raw images but, rather, much more concentrated forms of information. In particular, when the on-sensor image processing facilities are powerful enough to allow some structural pattern recognition, lists of pixels of interest become an output format of choice from retina to microprocessor. This implies the development of specific output techniques and operators to be integrated in the focal plane. After an in-depth presentation of the motivations in the context of programmable artificial retinas (PAR) for robot vision, two original solutions to the problem are presented, corresponding to two different trade-offs between efficiency and VLSI implementation cost. The first one is a compact hardware solution, which allows to sense pixels of interest from the sides of the 2D pixel array. The second one, a mainly software technique, exploits the mathematical concept of de Bruijn arrays for a distributed encoding of pixel addresses on the PAR.

An artificial retina intimately associates an imager with processing facilities on the same VLSI circuit. We investigate how a priori structural knowledge can be exploited to analyse raw image data within such a device. Massive parallelism together with severe VLSI constraints lead to original choices regarding information representation and processing. In particular, it is explained why and how the respective potentialities of analog and digital hardware can be advantageously combined within the retina microcosm. As an exemplary application, we then concentrate on and illustrate the problem of object contour tracking.>

Because binary representation of images fit VLSI constraints well, the bilevel rendition of continuous tone pictures, referred to as the halftoning problem, is likely to play an important role in robot vision soon. In the present work, the author explains (in 1-D) and puts in evidence (in 2-D) an important limitation of the most familiar high-quality technique, i.e., error diffusion. By extending earlier work of B.M. Gray (1989), it is shown that the full propagation of the error on uniform images may generate a significant amount of low-frequency spectral energy, which corresponds to the appearance of undesirable textures and artifacts on the halftoned image. Disagreeing with results presented by R.A. Ulichney (1988), the author concludes that error diffusion is a bad 'blue noise' generator. Relaxing the DC constraint through an optimization approach solves the difficulty.>

A smart retina is a device which intimately associates an optoelectronic layer with processing facilities. The rapprochement between acquisition and processing is particularly suited for the emergence of novel kinds of interaction, between analog and digital massive computations. Therefore, several attempts of analog, possibly neural, computations linked to the vision process are listed and discussed. But analog is not enough for really smartening retinas. Then, an additional plausible coat of cellular boolean iterative processing in these 'human size' vision machines is described, and commented on through examples.>

The author present his halftoning technique as an analytical 2-D extension of Sigma - Delta modulation, which is proven to feature optimal characteristics for the halftoning problem. A particular effort is devoted to transforming the sequential expression of Sigma - Delta modulation into a parallel and dimension-independent expression. This allows a precise understanding of the halftoning action in the frequential domain, while explaining the good experimental performance of the method.>

Halftoning is presented as an application where the use of simple neural networks proves to be of immediate interest. Halftoning is a nonstandard A/D conversion that is treated as an optimization problem, subject to a frequency-weighted mean-square-error (MSE) criterion. The frequency weight is implemented by means of a specific neural interconnection network based on current diffusion in resistive grids. This physical choice not only leads to a dramatically compact VLSI switch capacitor implementation, but also turns the whole process into a clean 2-D isotropic generalization of Sigma - Delta modulation. Isotropy and shift-invariance cooperate within the same halftoning process for the sake of image rendition. The performances prove equal to the deep underlying harmony between the theoretical, algorithmic, and material aspects of the procedure.>

The design of a compact and parallel cellular array featuring minimal-size Boolean processors as with optoelectronic devices and nonstandard A/D (analog/digital) converters is discussed. This human-size vision machine is called Retina, which is to be integrated on a single monolithic CMOS circuit. It is shown that the rapprochement between acquisition and processing is particularly suited for the emergence of unique kinds of interactions between analog and digital computations. The immediate interest of analog neural computations for the nonstandard A/D conversion implied by the Retina structure is emphasized. The optimality of the corresponding process is shown. However, the authors claim that, within smart sensors, pattern recognition is better carried out by an iterative Boolean computational scheme.>