With the development of cloud technology, people are focusing on lightweight container technology. Container networking is a core technology in providing high-level cloud services, and there are various implementation models such as Container Network Model (CNM) and Container Network Interface (CNI). Among them, CNI is a de-facto standard adopted by various container platforms. There are many plugins that implement the CNI networking model, and the implementation method differs, showing a great difference in a view of performance. MEC (Multi-Access Edge Computing) is a technology that provides services by locating the server closest to the user who wants to use mobile communication services. In this paper, the performance was measured by applying various CNI network plugins to the CoV architecture. Through this measurement, we analyzed the factors of network performance degradation. The result of the analysis is expected to be used as a good reference in constructing the CoV architecture for low latency in the future.

Content Addressable Memory (CAM) is beneficial to applications that require high-speed pattern searching as it provides fast associative lookup operations. As the amount of data to search continues to grow, reducing power consumption while minimizing the costs for speed and area is the main thread of research in designing large capacity CAMs. In this work, we are presenting an active memory architecture incorporating a searchable resistive memory. The proposed architecture incorporates processing logic in close proximity to the RRAM and the RRAM-based TCAM, where the unit TCAM cell is comprised of five transistors and two memristors. Analyzed and simulated performance (e.g., latency, energy consumption, and storage density) of the RRAM-based TCAM at various technology nodes are presented and compared to those of prior CAM/TCAM designs.

A memristor-based architecture for neuromorphic computing is proposed. With memristors mimicking key characteristics of synapses and neurons, such nanoscale neural networks exhibit learning and memory effects with high integration density and scalability. Simulations demonstrate important features including adjustable spike generation, spike-timing and spike-rate dependent plasticity.

A memristors-based Ternary Content Addressable Memory (mTCAM) is presented. A unit mTCAM cell consists of 5T2R, five transistors and two memristors to store the ternary information, having higher storage density than conventional CMOS TCAMs together with the memristors' unique non-volatility. In the write mode, each memristor in the cell is programmed individually such that high impedance is always present between searchlines to reduce the direct current. A two-step write scheme is proposed to reduce the write voltage compliance, and the search voltage used to drive the search content was chosen to optimize the sensing margin. Simulation results for a 2×4 mTCAM array demonstrate the functionality and feasibility of the proposed mTCAM structure, in both write and search modes.

A unified modeling approach is proposed to cover a broad range of memristive devices. The modular structure of the model enables it to represent behaviors of different types of devices. Resulted from theoretical analyses, the window function is uniquely controlled by the memristive flux. This not only solves the stability problem at boundaries present in previous models, but also reveals that an equivalent charge-flux constitutive relationship can be obtained from various types of memristive devices. Simulations on three device examples show that our model exhibits the device properties such as the frequency-dependent hysteresis, the limited memductance switching range with boundary assurances, the linear/nonlinear dopant drift, and the threshold voltages for read/write mode.

New memristors-based resistive logic computation units are introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed output can be accessed anytime later on by reading the output memristor's state. The memristive multiplier circuits demonstrate a fast correlation computing for highly complex inputs.

In this paper, a 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n x m passive memory arrays of memristive devices. This data-dependent 2 × 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 × 128 passive array with OFF-to-ON resistance ratio of 103.

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. Due to the fine grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required. We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding.

This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarity written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with limited resistance ranges, a simple method to find their constitutive relationships is discussed, and examples of compact models are shown for both current-controlled and voltage-controlled memristors. Our models satisfy all of the memristor properties such as frequency dependent hysteresis behaviors and also unique boundary assurance to simulate memristors whether they behave memristively or resistively. Our models are implementable in circuit simulators, including SPICE, Verilog-A, and Spectre.

We measured the capacity for VoIP traffic in an IEEE 802.11b wireless testbed and compared it with the theoretical capacity and our simulation results. We identified factors that have been commonly overlooked in past studies but affect experiments and simulations. We found that in many papers, the capacity for VoIP traffic has been measured via simulations or experiments without considering these factors, showing different capacity in each paper. After these corrections, simulations and experiments yielded a capacity estimate of 15 calls for 64 kb/s CBR VoIP traffic with 20 ms packetization interval and 38 calls for VBR VoIP traffic with a 0.39 activity ratio. Furthermore, we measured the capacity for VoIP traffic using each access category introduced in the 802.11e standard and the effect of the TCP traffic on VoIP traffic. We found that while the 802.11e standard can protect the QoS of VoIP against TCP traffic, it does not improve the capacity due to the significant retransmissions during TXOP.

As IEEE 802.11 networks in a BSS are increasingly used to carry VoIP, concerns about QoS arise. The overall delay of all VoIP flows drastically increases when the number of VoIP sources approaches the capacity, due to the characteristics of CSMA/CA. We propose a novel call admission control with the Queue size Prediction using Computation of Additional Transmission (QP-CAT) to avoid admitting an excessive number of simultaneous calls. In QP-CAT, an AP can accurately predict the effect of new VoIP flows on the delay of existing VoIP flows by predicting its queue size, before the new VoIP flow is actually admitted. It can be easily extended to support 802.11e so that the AP can predict the effect even when background traffic exists with VoIP traffic under 802.11e.

This paper describes a radio architecture and circuit implementation results for Korea/Japan standards of 5.8 GHz DSRC systems. By characterizing specific system features concerning practical environments such as communication cell area and in-vehicle temperature, we extract detailed design specifications and show a practical system implementation. Also, we introduce a new receiver sensitivity control method which has superior signal quality over the conventional ones by gating the detected RX data with respect to the received RSSI, without degradation of receiver SNR. When the complete transceiver circuit is integrated on a chip using 0.18 mum CMOS technology, the transmitter carries up to +10.5 dBm of output power and the receiver has less than 17 dB of system noise figure. The active current consumptions are 102 mA and 52 mA during TX- and RX- modes, respectively, for 1.8V supply voltage.

We measured the capacity for VoIP traffic in an 802.11b test-bed and compared it with the theoretical capacity and our simulation results. We identified factors that have been commonly overlooked in past studies but affect experiments and simulations. We found that in many papers the capacity for VoIP traffic has been measured via simulations or experiments without considering those factors, showing different capacity in each paper. After these corrections, simulations and experiments yielded a capacity estimate of 15 calls for 64 kb/s CBR VoIP traffic with 20 ms packetization interval and 34 calls to 36 calls for VBR VoIP traffic with 0.39 activity ratio.

During a layer-3 (L3) handoff, address acquisition via DHCP is often the dominant source of handoff delay, with duplicate address detection (DAD) responsible for most of the delay. We propose a new DAD algorithm, passive DAD (pDAD), which we show to be effective, while introducing only a few milliseconds of delay. Unlike traditional DAD, pDAD also detects the unauthorized use of an IP address before it is assigned to a DHCP client.

This paper describes a high speed current mode multilevel simultaneous bi-directional I/O which calibrates pin-to-pin current mismatch. Output impedance is controlled by an impedance matching circuit reducing process variation down to /spl plusmn/2.5%. Maximum 20% pin-to-pin current mismatch is reduced to 1.25% by 4-bit digital calibration scheme. Simulation results based on 0.18/spl mu/m CMOS process show that the proposed design achieves 4-Gb/s/pin data rate with 512ps timing window and 27mV voltage window. I/O circuits consume 12mW/pin at a supply voltage of 1V.

This paper describes a radio architecture with fast analog frequency offset cancellation loop which is based on a /spl Sigma//spl Delta/ fractional-N frequency synthesizer and a frequency offset detector. The offset detector is composed of a frequency/phase detector (PFD) and a new non-uniform resolution time-to-digital converter (TDC). By adopting the weighted delay-length for the TDC, only 60-DFFs are used to generate digitized timing difference of 250ns with a minimum resolution of 1ns. For the 2.4GHz ZigBee transceiver with 4MHz IF, designed for 0.18/spl mu/m CMOS process, the frequency offset cancellation time takes about 30/spl mu/s under the PLL loop-bandwidth of 100 kHz.

A fully-differential quadrature PLL with common-mode noise immunity has been developed by using a differentially controlled quadrature-VCO (Q-VCO) along with a differential charge-pump (CP). To increase the common-mode rejection ratio (CMRR) of Q-VCO, a simple bias shifting technique was used with accumulation-depletion mode MOS varactors. The measured minimum CMRR of the Q-VCO control gain is more than 30dB and the frequency tuning range is 26.3% around the 2.5GHz center frequency with a 3-bit capacitor bank array. To reduce the overall power consumption, an architectural optimization and an inter-stage impedance matching (ISM) techniques were used in frequency divider circuits. Our frequency synthesizer was fabricated in a 1P6M 0.18/spl mu/m RFCMOS process, and the measured phase noise is -112dBc/Hz at 1MHz offset from the 2.458GHz output frequency while the total PLL current consumption is 8.2mA for 1.8V supply voltage.

In IEEE 802.11 wireless networks, the downlink delay rises as the number of VoIP nodes increases while the uplink delay remains small due to the same chance of media access between nodes and the Access Point (AP). This degrades the capacity and QoS of VoIP significantly. Therefore, we introduce Adaptive Priority Control (APC) to balance the downlink and uplink delay of VoIP traffic at the MAC layer, by giving to the AP a higher transmission priority, which is adaptively decided according to the uplink and downlink traffic volume. And, we verify through theoretical analysis that APC is an optimal method to balance the uplink and downlink delay.

With the deployment of IEEE 802.11 networks, supporting real-time traffic with stringent quality of service (QoS) requirements on these networks becomes a critical issue. We propose two new media access schemes, namely dynamic point coordination function (DPCF) and modified DPCF (DPCF2). These can improve the capacity for voice-over-IP (VoIP) traffic by up to 20% in IEEE 802.11b networks. We show how we can also achieve a drastic improvement in the end-to-end delay with mixed VoIP and data traffic. Delay is kept around 100 ms in heavily loaded traffic conditions with an average value under 60 ms in normal traffic conditions.