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Eric Lemoine

dblp:88/4952 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 1 heaviest of 1, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA-based network processing
FPGA-based pattern matching
0.011994
High Speed Pattern Matching in Genetic Data Base with Reconfigurable Hardware · ISMB 1994

Methods — techniques the papers use, named apart from their topics

reconfigurable hardware · 0.0
YearPublicationVenuePosition
1997 High speed intelligent machine through programmable hardware: application to genomic systems
abstract
The paper proposes a new technology for intelligent machines based on the concept of programmable hardware. To build an intelligent system, the designer has to adapt it to the problem. First we show that programmable hardware is an intermediate step for building configurations, in order to choose the best architecture. In this case, the tasks are performed in a time period that respects human cognitive capacities. Next is detailed a multi level model composed of the cognitive, software and hardware levels. An experimental platform has been built, based on programmable hardware, and used in a "Grand Challenge" problem: knowledge discovery in genetic sequence databases, to compare the relative efficiencies of programmable hardware and classical Von Neumann based architecture. Programmable hardware is shown to have a significantly faster response time, which is essential for modern day intelligent machine user interaction.
Eric Lemoine, Laurent Maillet-Contoz, David Merceron, Jean Sallantin
KES (2)1
1996 MATISSE: A Multimedia Web DBMS
Sheldon J. Finkelstein, Eric Lemoine, René Lenaers
EDBT2
1995 Run time reconfiguration of FPGA for scanning genomic databases
abstract
This paper evaluates the feasibility of reconfiguring an FPGA at run time, and tests its performance using a "Grand Challenge Problem", the high speed scanning of genomic sequence databases. Algorithm implementation into a XC3090 FPGA is described, and methods proposed for generating a placed Xilinx Netlist File that can be efficiently routed at run time by the Automated Placing and Routing Xilinx tools, in order to increase the speed and the density of the design. The same algorithm carefully optimised on a RISC processor has been compared with the run time reconfigurated FPGA, and shows the latter to have an improvement in speed of two to three orders of magnitude.
Eric Lemoine, David Merceron
FCCM1
1994 High Speed Pattern Matching in Genetic Data Base with Reconfigurable Hardware
Eric Lemoine, Joël Quinqueton, Jean Sallantin
ISMB1
1993 Reconfigurable hardware for molecular biology computing systems
abstract
The authors explore the scope of possibilities of the implementation of molecular biology algorithms on a reconfigurable hardware based architecture. In order to demonstrate both the flexibility and power of reconfigurable hardware, two algorithms have been implemented on an architecture constituted by 23 FPGAs (Xilinx XC3090) and 4MB of SRAM. These two algorithms have been chosen because of their biological relevance. One is a classical dynamic programming algorithm that is implemented as a monodimensional systolic array. The other, as described in this paper, is based on pattern detection in long sequences of letters. This algorithm has been implemented as a rapid content addressable memory. It is important to stress the fact that these performances are achieved thanks to the use of the entire possibilities of reconfigurability. This enables one to exploit to the full each level of parallelism of the algorithm. The concept of reconfigurable hardware perfectly suits the needs of molecular biology. The performances demonstrated in this paper are several magnitude orders greater than a 40 MIPS workstation.>
Eric Lemoine
ASAP1