Abstract In the design of integrated circuits, one critical metric is the maximum delay introduced by combinational modules within the circuit. This delay is crucial because it represents the time required to perform a computation: in an Arithmetic Logic Unit, it represents the maximum time taken by the circuit to perform an arithmetic operation. When such a circuit is part of a larger, synchronous system, like a CPU, the maximum delay directly impacts the maximum clock frequency of the entire system. Typically, hardware designers use static timing analysis to compute an upper bound of the maximum delay because it can be determined in polynomial time. However, relying on this upper bound can lead to suboptimal processor speeds, thereby missing performance opportunities. In this work, we tackle the challenging task of computing the actual maximum delay, rather than an approximate value. Since the problem is computationally hard, we model it in answer set programming (ASP), a logic language featuring extremely efficient solvers. We propose non-trivial encodings of the problem into ASP. Experimental results show that ASP is a viable solution to address complex problems in hardware design.

Emerging nanotechnonologies such as ambipolar carbon nanotube field effect transistors (CNTFETs) and silicon nanowire FETs (SiNFETs) provide ambipolar devices allowing the design of more complex logic primitives than those found in today's typical CMOS libraries. When switching, such devices show a behavior not seen in simpler CMOS and FinFET cells, making unsuitable the existing delay fault testing approaches. We provide a Boolean model of switching ambipolar devices to support delay fault testing of logic cells based on such devices both in Boolean and Pseudo-Boolean satisfiability engines.

Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection. We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences.

Summary form only given. Weighted pseudorandom test generation (WPRTG) uses test sequences characterized by non-uniform distributions of test vectors in order to increase the detection probability of random resistant faults. Such non-uniform distributions are characterized by the values of signal probability of the CUT inputs (weights). Since different faults may require different distributions, a (small) number of distributions is typically used. The weights of such distributions are identified by analyzing the CUT The corresponding pseudorandom sequences are typically obtained by inserting a combinational network between the TPG and the CUT. Differently from the genetic-based approaches, where only numerical coefficients are computed, we have used an evolutionary programming (EP) algorithm that directly evolves the WGU network. In fact, evolutionary approaches have been shown to be effective in the design of digital circuits. In particular, we evolve a population were each individual represents a possible WGU and the fitness function considers the fault coverage as a primary target and the test length and the cost of the WGU as secondary ones. The fault coverage is evaluated here by means of fault simulation.

Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage metric. Conditions are defined to ensure that (under steady-state conditions) either a fault is detected by a test sequence or it will not give rise to errors for any other input, independently of the actual values of IC parameters. Such a fault model has been implemented in a simulator and validated over combinational benchmarks.

Design methodologies based on reuse of intellectual property (IP) components critically depend on techniques to protect IP ownership. IP protection is particularly challenging for hardware/software systems, where an IP core runs embedded software: both the software and the core are valuable IP that must be protected.

Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components.

One key issue in design flows based on reuse of third-party intellectual property (IP) components is the need to estimate the impact of component instantiation within complex designs. In this paper we introduce JavaCAD, an Internet-based EDA tool built on a secure client-server architecture that enables designers to perform simulation and cost estimation of circuits containing IP components without actually purchasing them. At the same time, the tool ensures intellectual property protection for the vendors of IP components, and for the IP-users as well. Moreover, JavaCAD supports negotiation of the amount of information and the accuracy of cost estimates, thereby providing seamless transition between IP evaluation and purchase.

This paper presents JavaCAD, a new Java-based CAD framework for the design, validation and simulation of systems using third-party components with reciprocal intellectual property (IP) protection. The designer can use remote components with a dedicated and secure Internet protocol, that guarantees IP protection and supports a smooth transition between component evaluation and purchase.

At different design levels, testability is becoming more and more important since high levels of reliability are required by many applications. In this work, a novel approach to the mapping between signal lines and gate inputs is proposed, targeting the I/sub DDQ/ testability of internal faults. Suggesting an additional cost function for the routing process, the method provides significant testability enhancements without affecting either the gate-level structure of the circuit or the internal layout of the gates, as proved with regards to bridging faults.

A new BIST scheme suitable for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be selectively changed by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for self-test when data retention must be checked.

This paper presents a fault model, called node-break fault model, to effectively account for broken connections inside CMOS circuits. The proposed model is very general since it allows to generate test vectors for broken connections that cannot be detected by means of test sequences for stuck-open faults. In addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node, thus superseding the stuck-open fault model. The model can be used to derive tests and to perform fault simulations independent of the actual layout of the circuit. Conditions for the detection of broken connections are derived from electrical considerations (aimed at verifying the presence of electrical continuity between the terminals of transistors connected to a node) while the minimum number of input vectors to test for broken connections in a node is determined by graph theory. Fault simulations performed on benchmark circuits using test sequences oriented to the detection of stuck-open faults show their inadequacy in detecting node-break faults, thus claiming for considering such a fault model in the test pattern generation.

So far, the test pattern generation for I/sub DDQ/ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during the fault activation, in such a way that either a higher fault coverage can be obtained or a less accurate sensor can be used.

This paper presents a study of the dynamic behavior of CMOS and BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering delay fault testing and results are compared with those achieved by means of functional testing. Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection as delay faults of bridging faults in BiCMOS circuits is more difficult than in the CMOS case.>

The authors point out that the simulation of resistive bridging faults inside complex CMOS macrogates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. Here, an approach applicable to a large category of faults (bridgings, transistor stuck-ons, and node stuck-ats) that give rise to resistive paths between power supply and ground, and hence are all covered by the general term 'bridging faults,' is presented. This method, which avoids the single-fault-injection procedure, fault analysis is performed inside the macrogates aimed to determine the threshold resistance, thus discriminating whether or not a given fault is detectable as a logic error. This analysis is performed inside CMOS macro-gates whose output is observable. To fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults.>

This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring.>

This paper presents a new approach to the fault simulation of parametric bridgings in CMOS ICs synthesized by means of libraries of macro-gates. The method is based on a fast but accurate preliminary characterization of any macro-gate for each input set. Such a characterization provides all information to determine, during the actual fault simulation, the maximum value of resistance for any considered bridging that makes the fault observable at a circuit primary output. This library characterization is very general, and can be used with any fa.ult simulation technique. Results on several benchmarks show that this approach allows the fault simulation of internal parametric bridging faults in a time comparable to that of the classical line stuck-ats.

This paper analyzes the effects induced on the electrical behavior of BiCMOS digital circuits by bridging faults, whose instrinsic resistance value is shown to have a strong impact on the static behavior of faulty gates and of their fan-out gates. The problem of fault detection is then addressed considering two different testing techniques (current monitoring and functional testing). Simulations of the electrical behavior of faulty BiCMOS circuits have enlightened the main differences with respect to the CMOS technology: the larger driving capability of BJTs with respect to MOSFETs makes the detection of bridging faults much more difficult in BiCMOS circuits when functional testing is considered, but more effective when current monitoring is used.