The authors propose a call admission control scheme based on a method of estimating cell loss quality for individual bursty traffic sources. The estimate is expressed in terms of virtual cell loss probability, which may be defined by two traffic characteristic parameters alone: peak and mean rate. The approach is suitable for the estimation of real cell loss probability in heterogeneous and homogeneous traffic models when burst length is larger than buffer capacity. The concept of virtual cell loss probability is extended to the individual call level so as to be able to estimate the quality of service (QOS) provided to individual calls. A virtual bandwidth method is used to develop a practical call admission control system. Quality is ensured by combining a traffic clustering scheme, with a scheme for assigning individual clusters to subcapacities of a link. Priority levels are presented in terms of the class of QOS required, i.e., deterministic or statistical, and the allocation of virtual bandwidth is discussed in terms of both QOS class and traffic characteristics.>

The authors discuss and propose a very-high-speed and high-capacity packet-switching (HPS) architecture for a future broadband ISDN (integrated-services digital network). The HPS network accommodates various communication services, such as voice, high-speed data, high-speed still picture, and video services. The proposed architecture has three significant principles: a high-speed oriented simple network protocol, separation of signaling and network control from data transfer, and hardware switching. These principles provide fast- and high-throughput transmission for data packets and reliable transmission and processing for call-control packets. The HPS protocol structure is addressed, which provides high flexibility for various communications services as well as high-speed capability. A 3-Gb/s capacity and building-block-structured packet-switching system architecture, using bus- and loop-type switch fabric, is also presented.>

A new switching architecture for broadband ISDN, "Synchronous Composite Packet Switching (SCPS)," is proposed and evaluated. It efficiently integrates circuit and packet switching functions on a single switching system and accommodates very high speed-up to several tens of Mbit/s-communication services, such as very high speed bursts of data, still picture, and motion video, as well as 64 kbit/s or less voice and data services. The SCPS system comprises plural switch modules and plural Very high speed synchronous loops. In the SCPS system, messages on plural circuit switched channels are assembled into quasi-packets, called "composite packets," and switched synchronously between switch modules, maintaining complete time transparency and short absolute delay time. A system parameter design to obtain high system efficiency and appropriate system modularity is explained, and an example for a very large capacity transit switch of 4 Gbit/s throughput is presented. System implementation problems to realize the SCPS principle, such as efficient implementation of the composite packet assembling and loop transmission functions, are investigated and an experimental system constructed for circuit switching part is presented. The most remarkable characteristic of the SCPS is that it efficiently integrates64 \times nkbit/s circuit switching with packet switching. Moreover, the SCPS system retains compatibility with existing networks and the possibiliy of evolution toward a future broadband ISDN. On the basis of the above investigations and experimental system construction, the authors conclude that the SCPS is one of the most practical switching architectures for the coming broadband ISDN era.