Recent increases in VLSI processor speed and transistor density have not been matched by a proportionate increase in the number of I/O pins used to communicate information on and off chip. Since the number of I/O pins is limited by packaging technology and switching constraints, this trend is likely to continue, and I/O bandwidth will become the primary VLSI system performance bottleneck. This paper analyzes the potential of address and data stream coding in order to reduce bandwidth requirements

Abstract We describe the implementation and performance of a three dimensional particle simulation distributed between a Thinking Machines CM‐2 and a Cray Y‐MP. These are connected by a combination of two high‐speed networks: a high‐performance parallel Interface (HIPPI) and an optical network (UltraNct). This is the first application to use this configuration at NASA Ames Research Center. We describe our experience Implementing and using the application and report the results of several timing measurements. We show that the distribution of applications across disparate supcrcomputing platforms Is feasible and has reasonable performance. In addition, several practical aspects of the computing environment arc discussed.

The authors describe the implementation and performance of a three dimensional particle simulation distributed between a Thinking Machines CM-2 and a Cray Y-MP. These are connected by a combination of two high-speed networks; a high performance parallel interface (HIPPI) and an optical network (Ultra Net). This is the first application to use this configuration at NASA Ames Research Center. The authors describe their experience implementing and using the application and report the results of several timing measurements. They show that the distribution of applications across disparate supercomputing platforms is feasible and has reasonable performance. In addition, several practical aspects of the computing environment are discussed. >

We analyze the information content of several address reference streams.Our results indicate that a new scheme, based on Dynamic Huffman Coding [Vitt87], can encode a typical 32 bit address in four to seven bits.Unlike previous schemes used to estimate the information content of address words [HaDa771 ~arnm77], our scheme is completely on-line and does not rely on preeomputation of address transition probabilities.Our results imply that at least 83% of address bits in the traces we studied contain redundant information.Although our coding scheme is too complex and computationally expensive to implement in practice, it provides a lower bound on the bandwidth that can be achieved by practical compression schemes.Through use of these address compression techniques, the number of bus lines and 1/0 pins required to transmit address information between processor and memory can be ptly reduced.

This paper analyzes measurements of paging activity from several different versions of UNIX. We set out to characterize paging activity by first taking measurements of it, and then writing programs to analyze it. In doing so, we were interested in answering several questions:1. What is the magnitude of paging traffic and how much of I/O system activity is paging related?2. What are the characteristics of paging activity, and how can paging system implementations be tuned to match them?3. How does paging activity vary across different machines, operating systems, and job mixes?4. How well does paging activity correlate with system load average and number of users?