Debugging incurs significant costs in the semiconductor industry, with some engineers spending 40% or more of their time debugging. Despite the critical importance of this skill, undergraduate students often need help to develop it. In this paper, we administered a circuit debugging test to second and third-year electrical and computer engineering (ECE) students in an introductory microelectronics class. The buggy circuit was a non-inverting amplifier printed circuit board with a misoriented op-amp. The pilot results on 26 students revealed concerns about misconceptions and biases in their debugging methodology. 54% of students focused predominantly on scrutinizing resistors, neglecting a broader exploration of potential issues. Furthermore, 46% limited their search for errors to a single potential problem, and 15% could not accurately measure resistance. Ultimately, 31% successfully identified and corrected the bug, indicating exam expectations were achievable and giving us hope that debugging skills are within reach for our students. However, specialized training may be needed to get them there.

This work-in-progress research-to-practice paper presents the development and pilot implementation of curriculum that introduces semiconductor contents in a high school calculus class. The demand for chips soared through the COVID-19 pandemic, exposing our country's semiconductor manufacturing and supply chain risks. The need to reassert US semiconductor leadership will require training a well-educated workforce, starting at the K-12 level. Meanwhile, K-12 STEM teachers often juggle the conflicting requirements of standardized tests and the need to cultivate 21st-century skills, deeper learning, and transferable knowledge, among others. This paper presents a pilot implementation that could address both problems. Selected teachers attended an NSF-funded Research Experience for Teachers (RET) summer program to learn about chip design basics. They also received curriculum development support to design new modules on semiconductor topics that would attract their students' interests.

This summer, Oklahoma State University began a Research Experience for Teachers (RET) site focused on circuit design and semiconductors. Our work with math educators led to the development of lesson plans incorporating semiconductors and circuits to offer real-world examples in place of more abstract word problems. Through this effort we expect to improve math engagement of high school students and introduce them to valuable semiconductor topics. The inclusion of circuit and semi-conductor topics also begins the workforce development needed to fill the jobs projected to be created by the CHIPS Act. Real-world examples developed focus on diode and MOSFET models as applications of piecewise functions in Algebra I and inductor and capacitor circuits as applications of the Fundamental Theorem of Calculus.

This paper presents the first Research Experience for Teachers (RET) site in the United States on integrated circuit (IC) design and education for high school and community college teachers. Motivated by the enormous upcoming semiconductor workforce demand spurred by investments from the CHIPS and Science Act, we offered a six-week paid RET program for ten teachers in Oklahoma to learn about semiconductors and chip design. Teachers were also required to translate their experience into new curriculum modules. Our training leveraged the web-based Silicon Layout Wizard (Siliwiz), Wowki template, and the Tiny Tapeout flow, all running in a browser using the open-source Skywater 130 nm CMOS process. We also provided curriculum design training so teachers could teach the new materials more effectively. Among the ten participants, six successfully submitted their GDS files for fabrication. Four presented at the 2023 ASEE virtual poster sessions. Evaluation data indicated the challenges teachers initially faced and the enthusiasm they sustained throughout the RET program.

Side-channel attacks (SCA) pose significant threats to the hardware security of embedded devices. Various logical and circuit-level countermeasures propose security, but they all come with different power, performance, and area overhead. Besides countermeasures cannot guarantee security, if the adversaries have enough time and computing power in hacking. Thus, highly accurate, real-time attack detection techniques are needed. This paper proposes a switched-capacitor circuit that can detect power SCAs by intrusion detection of a current sense resistor in the external power supply line. A pulsed current is pulled on the supply line to introduce a voltage difference proportional to the IR drop. This IR drop is then amplified through a parasitic- insensitive switched-capacitor amplifier and compared against a pre-determined threshold. The circuit achieved a 4.01us typical detection time and better than 72% accuracy, consuming 2.97 mW in 65-nm CMOS. This work is the first mixed-signal IC implementation for power SCA detection. Compared to prior approaches that monitor the entire on-chip power grid, this circuit is more computation- and energy-efficient. It uses a single sensor with no need for data mining or machine learning classification.

In modern integrated circuits design, security is a significant concern due to power analysis based side-channel attacks. Various countermeasures such as hiding and masking have limitations, for example, performance degradation, power consumption, low scalability, and area overhead. Besides, these countermeasures cannot detect attacks and alert users to take protective steps against attack. A power side-channel attack (P- SCA) detection system is proposed in this paper through battery impedance monitoring. Due to malicious probing, a non-typical impedance change occurs in the battery. Therefore, our system monitors the battery impedance change to detect such attacks. The detection circuit consists of a 10 bit ADC, an S8050 NPN transistor, a 1N4007 diode, and sense resistors (10 Ω, 50 Ω, 1k Ω). The detection system is designed in an Arduino. Measurements show that the system can detect a P-SCA in 22.020 ms, which is well within the desired detection window. The desired detection windows for different sense resistor values are measured as well. The accuracy and power consumption of implementation are also analyzed.

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

Safety has become extremely important, even when the market is demanding faster charging of mobile batteries. Single-chip battery chargers cannot safely deliver the current needed because power density will exceed the package limit and create thermal hot spots. Therefore, a master-slave battery charging system using parallel DC-DC converters is presented. The master charger acts as a voltage or current source, and multiple slave chargers are turned on and off by the master as current sources. With it, the heat is spread out into multiple locations on the PCB, effectively eliminating thermal hot spots. With one slave, the constant-current (CC) phase charging time was reduced by 46%. With two slaves, thermal hot spots temperature were reduced by 15C. Designed as a switch-mode current source, the slave charger achieved 4% current accuracy (6-σ), and 92% peak efficiency from 5-9V input, 0.5-3A output range. It occupies 3.9 mm2 in a 0.18 μm BCD process.

A persistent-if less glamorous—challenge in hospitals lies in the day-to-day work of moving and lifting patients with impaired mobility. This is a challenge intensified by our burgeoning aging population, the obesity epidemic, and our aging healthcare workforce. During manual patient handling, the predominant risk of staff injury is excessive back and shoulder loading. A mobile robotic nurse assistant (RoNA) is highly desired to enhance the efficacy and quality of care that nurses and their paraprofessional staff can provide. Such an assistant could improve a nurse's working conditions by off-loading some of his or her most physically demanding duties, thereby reducing the potential for self-injury or injury to the patient. Hstar Technologies is developing a revolutionary RoNA system that provides physical assistance to nurses in a hospital ward. The design of RoNA is a safe and robust system that works effectively in a hospital environment under direct and telepresence control by a nurse or physician. RoNA has a humanoid design featuring bimanual dexterous manipulators that employ a series-elastic-actuation (SEA) system. These electric actuators provide manipulator compliance, safety, flexibility and the strength to lift patients weighing up to 300lbs. RoNA also features an innovative humanoid upper torso, a unique mobile platform with holonomic drive and posture stability enhancement, intelligent navigation control with 3D sensing and perception capability, an intuitive and innovative human-robot interaction control interface, and a highly integrated plan for healthcare system assembly. We anticipate that robotic maneuvering assistants would increase job satisfaction, reduce lifting-related injuries, and extend the years of effective service nurses could render in hospitals. These effects would reduce hospital costs and ameliorate problems posed by the shortage of nursing staff.

This paper describes a new course on mixed-signal IC test engineering, jointly established by the Department of Electrical and Computer Engineering (ECE) of The Ohio State University and Texas Instruments. The course is motivated by the lack of qualified test engineers in industry and the absence of this education at the collegiate level. The course objective is to help student obtain the fundamental skills required for a mixed-signal IC test engineer. The course structure and laboratory developments are covered in details. Students feedbacks based on anonymous survey indicate that the goals are well met.

Energid is developing a realistic surgery simulator that delivers high fidelity visual and haptic feedback based on the physics of deformable objects. Modeling the interaction of surgical tools with soft biological tissue in real time poses challenges because the precise physical models of organs are not readily available, and the simulation of the behavior of tissue has a high computational burden. In this paper we present a realistic surgery simulation technique which inlcudes novel algorithms for simulating surgical palpation and cutting. We implement a meshfree numerical technique for realistic surgery palpation simulation. Simulation of surgical cutting is one of the most challenging tasks in the development of a surgery simulator. Changes in topology during simulation render precomputed data unusable. Moreover, the process is nonlinear and the underlying physics is complex. We propose a hybrid approach to the simulation of surgical cutting procedures by combining a node snapping technique with a physically based meshfree computational scheme.