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Ching-En Lee

dblp:88/5605 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Reconfigurable computing and FPGAs · 33%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › efficient inference
binarized neural network inference		 0.412019
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA · FPGA 2019
Reconfigurable computing and FPGAs
FPGA-based neural network inference		 0.412019
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA · FPGA 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator		 0.412019
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA · FPGA 2019
Machine learning › Efficient and distributed learning
model compression		 0.112019
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA · FPGA 2019
Machine learning › Efficient and distributed learning › model compression › quantization
network binarization		 0.112019
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA · FPGA 2019

Methods — techniques the papers use, named apart from their topics

redundancy analysis · 0.8binarized neural network · 0.8
YearPublicationVenuePosition
2019 Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA
abstract
Binarized Neural Network (BNN) removes bitwidth redundancy in classical CNN by using a single bit (-1/+1) for network parameters and intermediate representations, which has greatly reduced the off-chip data transfer and storage overhead. However, a large amount of computation redundancy still exists in BNN inference. By analyzing local properties of images and the learned BNN kernel weights, we observe an average of ~78% input similarity and ~59% weight similarity among weight kernels, measured by our proposed metric in common network architectures. Thus there does exist redundancy that can be exploited to further reduce the amount of on-chip computations.
Cheng Fu 0002, Shilin Zhu, Hao Su 0001, Ching-En Lee, Jishen Zhao
 FPGA4