A 23–29 GHz power amplifier (PA) based on a stacked field-effect transistor (FET) topology is proposed. To achieve higher output power and gain, the output stage employs a triple-stacked FET design. To improve stacking efficiency, neutralization capacitors are added between the differential common-source (CS) amplifiers to compensate for phase mismatches at the stack nodes. Round-table and vertical gate repetition techniques are applied to achieve a compact layout and enhance the PA’s power density. The proposed PA is fabricated using the 22nm FD-SOI process. Measurement results show that the proposed PA delivers a peak saturated power (Psat) of 19.6 dBm, with a core area of only 0.047 mm2, achieving a power density of 1936.2 mW/mm2.

The paper presents a comprehensive theoretical analysis of dual-input digital Doherty power amplifiers (DPAs) and outlines a specific design methodology. The theory explains how adaptive input signals affect the linearity and efficiency of the amplifiers, as well as the necessary adjustments to the operating point of the peaking amplifier. Using the analytical model, the paper offers guidance on adjusting the input signal to achieve the highest efficiency, ensuring that the carrier amplifier remains in saturation mode within the load-modulated region. It also discusses the maximum theoretically achievable efficiency for digital DPAs, which serves as a benchmark for comparing results with other amplifier topologies. Additionally, the paper proposes a practical approach for implementing the adaptive input algorithm during the measurement of modulated test signals. This method combines the measured response of the DPA with the theoretically derived optimal input signal splitting pattern, creating test signals for both the carrier and peaking input paths of the DPA. This effectively addresses unseen sources of nonlinearity by the theoretical model within the input signal bandwidth. Validation experiments were conducted on a 50W dual-input DPA designed for 5G wireless communication at 3.5 GHz, utilizing a 90 MHz modulated signal.

This article presents the design and miniaturization of a wideband monolithic microwave integrated circuit (MMIC) fully distributed efficient power amplifier (FDEPA). Distributed structure arrangement has been applied not only on the auxiliary power amplifier (PA) but also for the main PA. Hence, complicated and bandwidth-limited input matching networks (IMNs) and phase alignment networks are replaced by artificial transmission lines (ATMLs) to simplify the design and save the chip area. At the same time, due to the wide bandwidth characteristic of the distributed main PA, the power back-off (PBO) bandwidth shows good results compared with the conventional single common-source PA arrangement. Besides, a compact wideband on-chip quadrature hybrid power splitter is employed to achieve reasonable power division and phase control. As a proof of concept, an FDEPA prototype has been designed and fabricated in a commercial 0.25-μm GaN-on-SiC process. The chip size is only 3.6 mm×2.55 mm with all the necessary components. From the measurement results, throughout the working band of 3.1-5.5 GHz (56% fractional bandwidth), 40.3-41.6 dBm saturation output power (Psat), namely 1.16-1.58 W/mm2power density are achieved. The associated saturation drain efficiency (DE) is around 46%-55.4% and the 9-dB PBO DE is around 30.3%-47.2%. Under 100-MHz orthogonal frequency division multiplexing (OFDM) signal excitation with 8.5-dB peak-to-average power ratio (PAPR), 29.3%-44.5% average DE has been observed for the whole operating band, while the adjacent channel power ratio (ACPR) is better than -46.2 dBc with the digital pre-distortion (DPD).

In recent years, fully-connected hybrid beamforming (FC-HBF) architecture has aroused widespread interest for millimeter wave (mmWave) massive multi-input multi-output (MIMO) communication systems. However, the FC-HBF structure suffers from significant linearity deterioration, limiting its applications in actual mmWave transmitters. To resolve this issue, an effective digital predistortion (DPD) method utilizing analytical multi-input behavioral models is proposed in this paper for linearizing the FC-HBF system. Based on the nonlinearity analysis and behavioral modeling of the array response, three analytical multi-input models are derived by embedding the priori beamforming information in the predistorter. The complexity of the proposed analytical models is significantly reduced compared to the state-of-the-art. Numerical simulations and experimental measurement are carried out on a$4\times 64$mmWave FC-HBF array and$2\times 16$quasi-test platform respectively to validate the performance of the proposed DPDs against the state-of-the-art DPDs, which show significant linearization abilities to compensate for the nonlinear distortions of beam signals. The proof-of-the-concept validations in this paper indicate that the proposed scheme is fully capable of linearizing an mmWave FC-HBF array.

This article presents an ultra-broadband distributed efficient power amplifier (DEPA) with reactance compensation and adaptive biasing. It is illustrated that the bandwidth of the DEPA can be improved apparently by applying a shunt short-circuited stub at the combining point. The principle of such method is that the back-off impedance variation with frequency can be compensated by the reactance of the shunt stub. Besides, to get over the high gain compression of the conventional DEPA, an adaptive biasing scheme is proposed for the auxiliary PAs. A DEPA is implemented in a 0.25-$\mu \text{m}$GaN-HEMT process for validation. The shunt stub is realized by a LC tank equivalently for a compact size. The fabricated DEPA achieves a saturated output power of 41.5–43 dBm and an 8-dB back-off drain efficiency (DE) of 38%–46.8% from 1.8 to 5.4 GHz with a chip size of$3.2\times3.2$mm2. The fractional bandwidth (FBW) is up to 100%. Applying a 100-MHz LTE signal with an 8.5-dB peak-to-average power ratio (PAPR), an average DE of 35%–43% is measured over the entire bandwidth, and adjacent channel power ratio (ACPR) is better than −47 dBc after applying digital predistortion. To the best of our knowledge, the proposed DEPA demonstrates the largest FBW among all reported integrated back-off efficient PAs without using digital techniques or reconfiguration.

This article presents a 24–40-GHz broadband beamforming transmit–receive (T/R) front-end (FE) chip for the next-generation millimeter-wave (mm-wave) communication systems. To achieve multiband coverage in a single beamforming front-end IC, the proposed beamforming chip adopts a unified gain and phase control scheme as well as an asymmetric T/R switch circuit, which simplifies the system design and enables broadband operation in both directions. The vector-modulation-based unified phase and gain control (UPGC) scheme eliminates the standalone variable gain amplifier (VGA) in the front end. The bidirectional impedance transformation T/R switch reduces the insertion loss in the TX path and enables Class-F$^{-1}$operation to improve the bandwidth and efficiency. Based on the proposed UPGC scheme and T/R switch circuit, a high-performance mm-wave front-end chip is implemented using a 0.13-$\mu$m SiGe BiCMOS technology. The fabricated front-end chip achieves 12.9–16.9-dBm maximum output power in TX mode, up to 14.3-dB gain and 7.4–9.2-dB noise figure (NF) in RX mode over the frequency range of 24–40 GHz. In both TX and RX modes, the proposed chip achieved less than 0.4-dB rms gain error and 2.0$^{\circ}$rms phase error. A four-element dual-band phased array module is designed and tested to evaluate the performance of the proposed chip in the 28-and 38-GHz dual-band phased array.

In this article, a fully integrated 1.0–11.0-GHz wideband distributed power amplifier (DPA) monolithic microwave integrated circuit (MMIC) design is presented. Particularly, a coupled technique with bandpass (CTB) characteristic between the kth output node and the ($k+1$)th input node of amplification units (AUs) is adopted in the DPA design. It generates an additional signal reuse path (SRP) to reuse part of the output signal to superimpose the input signal, and then they will be reamplified to the output artificial transmission line (O-ATML). Moreover, due to the bandpass characteristic, the signal reuse can be manipulated to target the upper cutting edges of the working band to alleviate sharp gain and power roll-off. By carefully controlling the SRP, the overall gain, output power, and bandwidth are enhanced and extended. The systematic design approach for the DPA is detailed with circuit implementations and optimizations. To validate the proposed concept, a DPA MMIC prototype is implemented and fabricated in a commercial 0.25-$\mu $m gallium nitride (GaN)-on-silicon carbide (SiC) high-electron-mobility transistor (HEMT) process. It shows the compact layout within a die size of 3.36 mm2. Under 28-V VDD power supply, the measured results show a flat$14.8\pm 1.0$-dB small-signal gain with 10.0-GHz wide operating bandwidth and good impedance matching conditions. A saturated output power (${P} _{\text {sat}}$) of 7.25 W with peak power-added efficiency (PAE) exceeding 38.7% is achieved. The proposed DPA obtains around 1.54–2.16-W/mm2 power density associated with an average PAE of 34.5% over the entire frequency range.

This paper presents the analysis and design of broadband balance-compensated transformer baluns, suitable for silicon-based millimeter-wave (mm-wave) circuits requiring broadband high-quality balanced-unbalanced conversion. By introducing a mode-dependent lumped-element transformer model, a general center-tap-based balance-compensation method is proposed for transformer baluns, with two practical broadband compensation techniques derived. Several critical issues regarding the practical design of broadband balance-compensated transformer baluns are also discussed, including the parasitic effects in balance compensation, the consideration of windings’ turn number, and the balun design for impedance matching. As a proof-of-concept, three broadband balance-compensated transformer baluns, operating at different frequencies, are employed in a D-band frequency sextupler in [mode = text, reset-text-series = false]22 nm FD-SOI CMOS. The fabricated sextupler demonstrates a 5.1-dBm peak output power and [mode = text, reset-text-series = false]8.49% peak DC-RF efficiency at [mode = text, reset-text-series = false]145.5 GHz, and presents a 3-dB peak output power bandwidth ranging from qtyrange [mode = text,reset-text-series = false, range-units = single]127162 GHz with more than 37-dBc harmonic rejection ratio (HRR).

This paper presents a broadband Doherty power amplifier (DPA) using quarter-wavelength ($\lambda $/4) transmission lines with negative characteristic impedance. In conventional DPA designs, the load modulation network is frequency-dependent, leading to bandwidth limitation at the back-off power region. In this design, by integrating two$\lambda $/4 transmission lines with negative characteristic impedance into the main and auxiliary branches, the impedance at the back-off power can be manipulated to maintain high efficiency at back-off power over a wide frequency range. Thus, the operational bandwidth is extended. In circuit realization, the two negative characteristic impedance$\lambda $/4 transmission lines are replaced by paralleled negative LC components. Then, the negative capacitor is combined into the$\pi $-shaped impedance matching network, while the negative inductor is eliminated by introducing Norton transformation. For verification, a broadband DPA with a fractional bandwidth of 108.6% from 0.8 to 2.7 GHz is implemented. The measured saturated output power is 41.8-44 dBm. The saturated and 6-dB back-off power drain efficiencies are 47.6%-84.4% and 39.5%- 52%, respectively. A 20-MHz LTE modulated signal with peak-to- average power ratio (PAPR) of 7.5 dB is also applied to measure the fabricated DPA. After digital predistortion, the adjacent channel leakage ratio (ACLR) better than −45.35 dBc is achieved, and the measured average efficiency is higher than 40% within the operating band.

In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction.

This article proposes a broadband high-efficiency parallel-circuit (PC) class-EF power amplifier (PA) along with a quarter-wavelength stub for the first time. By adding a reactive element${X}$, the design space is expanded so that the impedance terminations of the fundamental and harmonics are no longer fixed points. Based on the broadband capability of the proposed structure, using a GaN HEMT transistor, a proof-of-concept circuit implemented with the Chebyshev impedance transformation network is designed and fabricated. Experimental results demonstrate a high-efficiency broadband PA operating from 2.6-3.9 GHz, with the average efficiency of 71.5%, the measured output power (${P}_{\textit {out}}$) of 38.8-40.9 dBm and the power gain of 8.5-10.6 dB.

Power amplifier (PA) models, such as the neural network (NN) models and the multilayer NN models, have problems with high complexity. In this article, we first propose a novel behavior model for wideband PAs, using a real-valued time-delay convolutional NN (RVTDCNN). The input data of the model is sorted and arranged as a graph composed of the in-phase and quadrature ( I/Q ) components and envelope-dependent terms of current and past signals. Then, we created a predesigned filter using the convolutional layer to extract the basis functions required for the PA forward or reverse modeling. Finally, the generated rich basis functions are input into a simple, fully connected layer to build the model. Due to the weight sharing characteristics of the convolutional model's structure, the strong memory effect does not lead to a significant increase in the complexity of the model. Meanwhile, the extraction effect of the predesigned filter also reduces the training complexity of the model. The experimental results show that the performance of the RVTDCNN model is almost the same as the NN models and the multilayer NN models. Meanwhile, compared with the abovementioned models, the coefficient number and computational complexity of the RVTDCNN model are significantly reduced. This advantage is noticeable when the memory effects of the PA are increased by using wider signal bandwidths.

In this paper, a novel multi-stream spatial digital predistortion (DPD) technique is proposed to model and linearize the fully-connected (FC) hybrid beamforming (HBF) transmitters. The proposed scheme solves the DPD implementation issue in the FC HBF array by estimating and linearizing the beam signals instead of the individual PAs. In FC HBF systems, significant intermodulation (IMD) between different transmit signals will be generated due to the analog beamforming and combining network upstream of the power amplifiers (PAs). The IMD beams will end up being radiated in different directions and some of them might fall in the linear beam directions. Therefore, multi-input DPD blocks using a practical multi-variable model are constructed for each RF chain to eliminate the complicated inner- and cross-channel IMDs of the beam signals. Simulations on a 4-stream 64-element FC HBF array and experimental tests on a 2-stream 4-element system are carried out to benchmark the proposed DPD technique against the conventional techniques. Better than 13 dB adjacent channel power ratio (ACPR) improvement and 12 dB normalized mean square error (NMSE) improvement have been achieved by the proposed DPD technique.

Highly efficient power amplifiers (PAs) and associated linearization techniques have been developed to accommodate the explosive growth in the data transmission rate and application of massive multiple input multiple output (mMIMO) systems. In this paper, energy-efficient integrated Doherty PA monolithic microwave integrated circuits (MMICs) and linearization techniques are reviewed for both the sub-6 GHz and millimeter-wave (mm-Wave) fifth-generation (5G) mMIMO systems; different semiconductor processes and architectures are compared and analyzed. Since the 5G protocols have not yet been finalized and PA specifications for mMIMO are still under consideration, it is worth investigating novel design methods to further improve their efficiency and linearity performance. Digital predistortion techniques need to evolve to be adapted in mMIMO systems, and some creative linearity enhancement techniques are needed to simultaneously improve the compensation accuracy and reduce the power consumption.