In this article, a compact differential data transfer link architecture for isolated sensor interfaces (SIs) and immune to common mode transients (CMTs) is presented. The proposed architecture shows low latency supporting high-speed transmission with a low bit error rate (BER) in the presence of CMT noise for applications, such as data acquisition, biomedical equipment, and communication networks. In transportation applications, motors and actuators are subjected to harsh environmental conditions, e.g., lightning strikes and abnormal voltage operations. These conditions introduce noise and can cause damage to small electronics due to high-voltage power surges. To ensure human safety and circuitry protection, a data transfer system must be implemented between high-voltage and low-voltage domains. The proposed design has been simulated using Cadence tools, and a prototype has been manufactured in a 0.18-$\mu $m CMOS process. The fabricated prototype consumes an effective silicon area of$37.2\times 10^{3}~\mu $m2and can sustain a breakdown voltage of 710 Vrms. Experimental results show that the proposed solution achieves a CMT immunity (CMTI) of 2.5 kV/$\mu $s at a data rate of 480 Mb/s with a BER of$10^{-12}$. The propagation delay is 3.9ns with a 4 ps/°C variation rate over temperatures ranging from$- 31~^{\circ }$C to$100~^{\circ }$C. Under typical test conditions, the BER reaches$10^{-15}$with a peak-to-peak data dependent jitter (DDJ) of 29.8ps.

In this brief, we present a data communication system for the capacitive digital isolator capable of sustaining a breakdown voltage of 1.27 kVrms. A pulse amplitude modulation (PAM) strategy is implemented as a signal transmission scheme for capacitive coupling for the first time. It enables a data rate of 0.68 Gbps using a smaller number of ON-chip isolation elements and physical links compared with other circuits. In addition, this scheme allows our design to work at low-frequency operations without the need of additional large-area capacitors. Moreover, a propagation delay of 1.9 ns has been measured with a total jitter (TJ) of 333 ps, and a 46.8-pJ/bit energy consumption at 1 Mbps is obtained. The achieved performance ensures the design integration capability with a wide range of power control applications, particularly industrial sensor interfaces.

We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148$\boldsymbol {\mu }\mathbf {V_{rms}}$input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14${\mu }\text{V}$. Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost${\pm 2\pi }$input phase range, the maximum operating frequency of the PFD is 1.32 GHz.

A CMOS Hall-based fully integrated isolation amplifier for differential voltage sensing is presented in this work. The design is fabricated in a$0.35 \mu \text{m}$CMOS process in which the high voltage (HV) side of the amplifier contains a coil driver while the low voltage (LV) side includes a Hall-effect sensor, low-noise amplifier, programmable-gain amplifier, filter, and chopper switches. Another Hall sensor performs the digital isolation using the on-off keying (OOK) technique for clock recovery. The introduced prototype achieves above 120 dB of isolation mode rejection (IMR) at 60 Hz and operates at a continuous isolation working voltage of 0.6 kV. It has also a maximum nonlinearity of 0.64 %, an input-referred offset of 1 mV, a 40 dB full-scale signal-to-noise ratio over a 40 kHz bandwidth, and a spurious-free dynamic range of 64 dB. The silicon area for each of the two separate dices employed for the HV and LV side of the isolation amplifier is 1 mm2with a power consumption of 7.6 mW and 9.9 mW respectively. The achieved miniaturized size of the isolation components, as well as their significantly low-power consumption, ensure the suitability of the proposed isolation amplifier for multi-channel readout circuit applications.

A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain amplifier, and anti-aliasing filter. Because of the miniaturized size of isolation components, this approach can be packaged in chip for industrial applications. This solution replaces the need of bulky/frequency dependent current transformers, complex isolation amplifiers with embedded analog to digital converters, and allows proposed sensors to be used in voltage and current sensing applications. The introduced prototype achieves an input referred offset of 1 mV, 50 dB full-scale signal-to-noise ratio in a 10 kHz bandwidth, and spurious-free dynamic range of 53 dB, while satisfying continuous isolation working voltage of 550 V.

This paper presents a front-end amplifier with a novel isolation technique. The proposed isolation technique employs a single on chip stacked spiral coils to generate a signal dependent magnetic field. Also, an integrated Hall effect sensor implemented under the coil detects the generated magnetic field, while achieving a minimum isolation working voltage of 430 V. In this configuration, no signal modulation is required and frequencies from DC to 50 kHz are transmitted over the isolation barrier. On the high voltage side, a single bit programmable gain instrumentation amplifier increases the 3-dB frequency of the common mode rejection ratio and supports input differential voltage ranging from -2.5 to 2.5 V. Also, on the low voltage side, a dB-linear PGA with 6 bits of gain setting adapt the signal to the input dynamic range of an ADC. Finally, a programmable second order Butterworth Anti-Aliasing Filter conditioned the signal before conversion.

Whereas the use of FPGAs in aerospace applications is increasing, concerns about its sensitivity to radiations more particularly the single event upsets (SEU) in SRAM-based FPGA is enhanced as well. To ensure hardness assurance, radiation sensitivity should be estimated at different stages of the system development cycle. In this paper, we present a multi-abstraction level signature generation based on fault injection using fault simulation, fault emulation and radiation testing in order to build an accurate representation of the design faulty behavior. These signatures, which can be seen as high-level fault models, help the designer make decisions on the use (or not) of rad-hard components and the adequate mitigation technique very early in the design process. Results from the different types of signatures are compared. It first shows that the type of resources used to implement a module (e.g. multiplier) may influence its behavior when affected by an SEU. It also reveals that most of the faulty values observed during radiation testing appear in the simulation-based and emulation-based signatures, but that their frequency of occurrence can differ. Finally, limitations of some commercial tools to identify critical bits are investigated.

This article presents an application of a recently reported IC trimming technique using laser diffused resistors to reduce the input referred offset voltage of a precision amplifier. A three stage precision CMOS operational amplifier topology is proposed utilizing laser-trimmable diffused resistors for post-fabrication trimming. The amplifier is designed to operate over an industrial temperature range (-40°C to +85°C) including process corners and utilizes an on-chip CMOS bias generation circuit to maintain a robust performance. The results of post-layout simulation of the complete circuit are summarized. The effects of the trimming technique on the input offset voltage of the amplifier are described. The circuit is designed using the TSMC 0.18μm CMOS process and operates from a single supply of 3.3 V.

The circuit design of a large area magnetic field sensor array (LAMSA) is described. This prototype is developed for applications in magnetic field mapping and tactile sensor arrays. To enable the production of such a large sensor system, redundancy schemes are implemented and a laser interconnection post fabrication technique is used for fault repairs. The design restructurable capabilities rely on local redundancy schemes for the sensor grid and global redundancy schemes for the surrounding control circuits. Experimental results obtained on a laser restructurable subarray of magnetic field sensor cells are shown. A study of the robustness of the local sensor grid redundancy schemes is presented.