Demo Data from EDBT 2026 / reviewers in the wild / expert
Zhixi Fang
dblp:88/599
· DBLP profile ↗
13ranked-venue papers
9as first author
0since 2021 · last 1990
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 10 · 7 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Parallel and multicore computing · 66% Interconnection networks and networks-on-chip · 16% High-performance computing · 15% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel scheduling
loop scheduling |
0.0 | 1 | 1990 | Dynamic Processor Self-Scheduling for General Parallel Nested Loops · IEEE Trans. Computers 1990 |
Parallel and multicore computing
parallel programming models |
0.0 | 1 | 1990 | Dynamic Processor Self-Scheduling for General Parallel Nested Loops · IEEE Trans. Computers 1990 |
High-performance computing › tensor computation
convolution |
0.0 | 1 | 1989 | On the Communication Complexity of Generalized 2-D Convolution on Array Processors · IEEE Trans. Computers 1989 |
Parallel and multicore computing › parallel algorithms
parallel algorithm design |
0.0 | 1 | 1989 | On the Communication Complexity of Generalized 2-D Convolution on Array Processors · IEEE Trans. Computers 1989 |
Interconnection networks and networks-on-chip
hypercube network |
0.0 | 1 | 1987 | Parallel Algorithms for Image Template Matching on Hypercube SIMD Computers · IEEE Trans. Pattern Anal. Mach. Intell. 1987 |
Parallel and multicore computing
parallel algorithms |
0.0 | 1 | 1987 | Parallel Algorithms for Image Template Matching on Hypercube SIMD Computers · IEEE Trans. Pattern Anal. Mach. Intell. 1987 |
Parallel and multicore computing
array processor |
0.0 | 1 | 1989 | On the Communication Complexity of Generalized 2-D Convolution on Array Processors · IEEE Trans. Computers 1989 |
Interconnection networks and networks-on-chip › network topology
mesh network |
0.0 | 1 | 1989 | On the Communication Complexity of Generalized 2-D Convolution on Array Processors · IEEE Trans. Computers 1989 |
Processor architecture and microarchitecture
SIMD |
0.0 | 1 | 1987 | Parallel Algorithms for Image Template Matching on Hypercube SIMD Computers · IEEE Trans. Pattern Anal. Mach. Intell. 1987 |
Methods — techniques the papers use, named apart from their topics
shortest-delay self-scheduling · 0.0guided self-scheduling · 0.0fetch-and-op · 0.0communication complexity analysis · 0.0parallel algorithm design · 0.0hypercube interconnection · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1990 | Cache or Local Memory Thrashing and Compiler Strategy in Parallel Processing Systems
Zhixi Fang |
ICPP (2) | 1 |
| 1990 | Dynamic Processor Self-Scheduling for General Parallel Nested LoopsabstractA processor self-scheduling scheme is proposed for general parallel nested loops in multiprocessor systems. In this scheme, programs are instrumented to allow processors to schedule loop iterations among themselves dynamically at run time without involving the operating system. The scheme has two levels. At the low level, it uses simple fetch-and-op operations to take advantage of the regular structure in the innermost parallel loop nests; at the high level, the irregular structure of the outer loops (parallel or serial) and the IF-THEN-ELSE constructs are handled by using dynamic parallel linked lists. The larger granularity or the processes at the high level easily justifies the added overhead incurred from maintaining such dynamic data structures. The use of guided self-scheduling (GSS) and shortest-delay self-scheduling (SDSS) in this scheme is analyzed.> Zhixi Fang, Peiyi Tang, Pen-Chung Yew, Chuanqi Zhu |
IEEE Trans. Computers | 1 |
| 1989 | Effective dynamic scheduling and memory management on parallel processing systemsabstractAn effective dynamic processor self-scheduling scheme is presented for general parallel program constructs in a restructuring compiler. In the program constructs, parallel loops, serial loops, if-then-else constructs and a generalization of fork-joins can be nested in an arbitrary order, and procedure calls can be involved in any level of the nested constructs. In parallel programs, a piece of the program code, such as loop iterations, is called a chore, which is considered to be a work unit in the program. In this scheme, processors schedule themselves to the chores dynamically at execution time without involving the operating system. Memory management is another issue addressed. Efficiency concerns dictate treating chore locality differently from procedure locality. As a corollary, the number of call frames required at any one time for a nonrecursive procedure is bounded by the number of processors.> Zhixi Fang, C. Robert Morgan, Peter Belmont |
COMPSAC | 2 |
| 1989 | A New Parallel Sorting Approach with Sorting Memory Module
Chuanqi Zhu, Zhixi Fang, Xiaobo Li 0001 |
J. Parallel Distributed Comput. | 2 |
| 1989 | Parallel clustering algorithms
Xiaobo Li 0001, Zhixi Fang |
Parallel Comput. | 2 |
| 1989 | On the Communication Complexity of Generalized 2-D Convolution on Array ProcessorsabstractSeveral parallel convolution algorithms for array processors with N/sup 2/ processing elements (PEs) connected by mesh, hypercube, and shuffle-exchange topologies, respectively, are presented. The computation time complexity is the same for array processors with different interconnection networks. The communication time complexity, however, varies from network to network, and is the main focus. It is shown that by using inter-PE communication networks efficiently, each PE requires only a small local memory, many unnecessary data transmissions are eliminated, and the overall time complexity (including computation and communication) of algorithms is reduced to O(M/sup 2/).> Zhixi Fang, Xiaobo Li 0001, Lionel M. Ni |
IEEE Trans. Computers | 1 |
| 1988 | Dynamic Scheduling and Memory Management for Parallel Programs
C. Robert Morgan, Peter Belmont, Zhixi Fang |
ICPP (2) | 4 |
| 1988 | Closure Properties of Certain Classes of Languages Under Generalized Morphic ReplicationabstractIn this paper a new language operator, a generalized morphic replication, is introduced. Let Ω be a finite set of morphisms and reversal morphisms from ∑* into Δ*, and ω be in Ω*. A morphic replicator is defined as follows: for each x in ∑* define ω(x) to be h1(x) … hm(x), where |ω| = m and ω = h1 … hm. A generalized morphic replication extends ω to languages by ω(L) = {ω(x): x is in L} and to sets W of morphic replicators, where W ⊆ Ω*, W(x) = {ω(x): ω is in W} and W(L) = UW(x), where the union is taken over all x in L. It is shown that the class of languages accepted in real time by a non-deterministic reversal-bounded multitape Turing machine, the class of NP, and the class of the recursively enumerable sets, are all closed under the generalized morphic replication when the morphisms and the reversal morphisms are, respectively, linear-erasing, polynomial-erasing, and arbitrary. Zhixi Fang, Jitender S. Deogun |
Comput. J. | 1 |
| 1987 | A Heuristic Algorithm for Conflict Resolution Problem Multistage Interconnection Networks
Zhixi Fang, Jitender S. Deogun |
ICPP | 1 |
| 1987 | Dynamic Processor Self-Scheduling for General Parallel Nested Loops
Zhixi Fang, Peiyi Tang, Pen-Chung Yew, Chuanqi Zhu |
ICPP | 1 |
| 1987 | Deadlock Prevention in Processor Self-Scheduling for Parallel Nested Loops
Zhixi Fang, Peiyi Tang, Pen-Chung Yew, Chuanqi Zhu |
ICPP | 1 |
| 1987 | Parallel Algorithms for Image Template Matching on Hypercube SIMD ComputersabstractThis correspondence presents several parallel algorithms for image template matching on an SIMD array processor with a hypercube interconnection network. For an N by N image and an M by M window, the time complexity is reduced from O(N2M2) for the serial algorithm to O(M2/K2 + M * log2 N/K + log2 N * log2 K) for the N2K2-PE system (1 ¿ K ¿ M), or to O(N2M2/L2) for the L2-PE system (L ¿ N). With efficient use of the inter-PE communication network, each PE requires only a small local memory, many unnecessary data transmissions are eliminated, and the time complexity is greatly reduced. Zhixi Fang, Xiaobo Li 0001, Lionel M. Ni |
IEEE Trans. Pattern Anal. Mach. Intell. | 1 |
| 1986 | Parallel Algorithms for 2-D Convolution
Zhixi Fang, Lionel M. Ni |
ICPP | 1 |