This paper reports results of a study to determine and compare the effectiveness of various techniques aimed at reducing memory interference in multiprocessor multi memory systems. A simulation model of a multiprocessor, driven by address traces, is used for evaluation purposes. Two approaches to interference reduction are considered, being the reduction of overlapping memory requirements through various memory allocation methods, and the use of local memory to reduce the request rate to shared memory. Both private and cache memory are considered for this purpose.

This paper presents a mathematical model for determining the extent of memory interference in multiprocessor systems. The model takes into account the numbers of processors and memory modules in the system and their relative service times, as well as the patterns of memory accesses made by the processors. The results predicted by the model are compared with simulation results and with results from other exact or approximate models, where these exist.