Continuing a tradition at the IEEE VLSI Test Symposium this new topic session presents two interesting talks on new emerging computing and testing techniques. The first talk focuses on carbon nanotube electronics while the second talk discusses about wafer level testing under magnetic field.

In recent years, a clear path towards larger-scale quantum processors has emerged to study and eventually exploit the power of quantum computers at scale. The rapid progress has been observed in quantum computers, semiconductor implementations, and new generation of application development. The speakers will provide a perspective on the numerous challenges and their perspective on the future.

BACKGROUND: DNA methylation plays a key role in developmental processes, which is reflected in changing methylation patterns at specific CpG sites over the lifetime of an individual. The underlying mechanisms are complex and possibly affect multiple genes or entire pathways. RESULTS: We applied a multivariate approach to identify combinations of CpG sites that undergo modifications when transitioning between developmental stages. Monte Carlo feature selection produced a list of ranked and statistically significant CpG sites, while rule-based models allowed for identifying particular methylation changes in these sites. Our rule-based classifier reports combinations of CpG sites, together with changes in their methylation status in the form of easy-to-read IF-THEN rules, which allows for identification of the genes associated with the underlying sites. CONCLUSION: We utilized machine learning and statistical methods to discretize decision class (age) values to get a general pattern of methylation changes over the lifespan. The CpG sites present in the significant rules were annotated to genes involved in brain formation, general development, as well as genes linked to cancer and Alzheimer's disease.

BACKGROUND: For many years now, binding preferences of Transcription Factors have been described by so called motifs, usually mathematically defined by position weight matrices or similar models, for the purpose of predicting potential binding sites. However, despite the availability of thousands of motif models in public and commercial databases, a researcher who wants to use them is left with many competing methods of identifying potential binding sites in a genome of interest and there is little published information regarding the optimality of different choices. Thanks to the availability of large number of different motif models as well as a number of experimental datasets describing actual binding of TFs in hundreds of TF-ChIP-seq pairs, we set out to perform a comprehensive analysis of this matter. RESULTS: We focus on the task of identifying potential transcription factor binding sites in the human genome. Firstly, we provide a comprehensive comparison of the coverage and quality of models available in different databases, showing that the public databases have comparable TFs coverage and better motif performance than commercial databases. Secondly, we compare different motif scanners showing that, regardless of the database used, the tools developed by the scientific community outperform the commercial tools. Thirdly, we calculate for each motif a detection threshold optimizing the accuracy of prediction. Finally, we provide an in-depth comparison of different methods of choosing thresholds for all motifs a priori. Surprisingly, we show that selecting a common false-positive rate gives results that are the least biased by the information content of the motif and therefore most uniformly accurate. CONCLUSION: We provide a guide for researchers working with transcription factor motifs. It is supplemented with detailed results of the analysis and the benchmark datasets at http://bioputer.mimuw.edu.pl/papers/motifs/ .

Power electronics covers various disciplines, especially semiconductor, circuit design, thermal design (heat transfer, fluid flow), electromagnetics (EMI, Inductors, transformers), digital electronics, control theory, and materials science in the context of packaging and reliability engineering. It also covers a wide range of power (mW to MW), temperature (−55C to 275C), frequencies (DC to GHz) and dimensions (um to km). The global power electronics market is worth over $200Bn and is seeing significant growth in sectors such as aerospace, automotive and energy generation, transmission and distribution. This presentation will discuss the current status and future challenges in the design of power electronics components and systems. In particular co-design in terms of the modeling and analysis toolsets that enable power electronics designers to undertake thermal, electromagnetic and mechanical analysis of new power electronics components and systems, as well as the need for an holistic approach to designing such systems from the devices to convertors and drives in an integrated manner.

MEMS sensors are driving the internet of things and the market for MEMS is growing rapidly. In many MEMS products, test strategies are not standardized, proprietary, and considered important intellectual property. However, an eco-system is beginning to form as equipment makers are developing dedicated MEMS test equipment and test houses offer services for testing MEMS. This talk describes the challenges and opportunities for MEMS testing. Current MEMS testing is compared to the established methods of VLSI test. The talk further describes how design for test concepts can be applied to MEMS design. Finally, testing MEMS integrated within larger systems is highlighted.

In this talk, a unitary perspective is given on the design challenges involved in ultra-low voltage (ULV) VLSI circuits and systems, as well as on directions to tackle them. Innovative approaches are described to improve the energy efficiency of ULV systems, while maintaining adequate resiliency and yield with low overhead. Experimental results based on the testing of 65-nm to 28-nm prototypes are presented to develop a quantitative sense of the achievable benefits. Emphasis is given on applications that require extremely high energy efficiency, such as compact portable devices and energy-autonomous VLSI systems. Although CMOS is the mainstream choice for the foreseeable future, Tunnel FETs (TFETs) are introduced as very promising alternative that favors more aggressive voltage scaling and energy reduction. Although still immature, device-circuit co-design is shown to be critical to the success of such technology. Potential of TFETs is discussed in a general framework through representative metrics and vehicle circuits, emphasizing how design will be impacted by their adoption.

Consider a re-spin of an existing complex SoC, with a partial schematic and an incomplete specification, with limited abilities to test and observe I/O behavior. Additionally, the underlying technology used is only partially understood. Can disciplined engineering approaches yield the re-spin? What are fundamental challenges? How will automation tools enable such designs? This talk will showcase how analysis and synthesis concepts can be applied in the context of biological discovery and design. Various optimization and analysis techniques can be applied to maximize the production of ethanol within an E. Coli cell without kill it. Pathway synthesis techniques can help uncover the fate of environmental chemicals within the human gut, which is colonized by ∼1014 bacteria belonging to ∼1000 species. No biology pre-requisites are needed to attend this talk.

We analyze the effects of faults on an energy-harvesting circuit (EHC) providing power to a wireless biomedical multisensor node. We show that such faults may prevent the EHC from producing the power supply voltage level required by the multisensor node. Then, we propose a low-cost (in terms of power consumption and area overhead) additional circuit monitoring the voltage level produced by the EHC continuously, and concurrently with the normal operation of the device. Such a monitor gives an error indication if the generated voltage falls below the minimum value required by the sensor node to operate correctly, thus allowing the activation of proper recovery actions to guarantee system fault tolerance. The proposed monitor is self-checking with regard to the internal faults that can occur during its in-field operation, thus providing an error signal when affected by faults itself.

Organic electronics, such as OLEDs, OPVs, and polymer based power storage units (batteries and capacitors) are rapidly becoming low-cost viable alternatives to silicon-based devices. These organic devices however, are still reliant on the support functions of standard silicon components such as power and logic transistors. Integration of these organic devices with standard silicon electronics into a combined heterogeneous system requires specific design and fabrication considerations. Full-scale integration with conventional silicon based electronic components is challenging due to their incompatibility with common semiconductor fabrication process that can damage the active organic compounds. The printable/spray/spin nature of organic electronics fabrication makes 3D integration an attractive methodology. We propose to combine the organic and inorganic portions of a heterogeneous system by fabricating the modules separately (hence enabling parallel manufacturing) in a specific 2D layout scheme, and subsequently connecting the devices together in a post fabrication process. In this paper we discuss the 2D designs in detail and propose a 2D-3D hybrid design as well as a fully 3D stacked design for organic electronics with energy storage devices in a face-to-back configuration. The fabrication process of each device and the integration of OPVs and OLEDs with power storage devices are discussed. An overview of test procedure and fault tolerances for the proposed configuration is provided. Finally, a potential solution for a new test environment derived from a mixed configuration of different technologies and materials is proposed.

This paper presents an ATE component-styled, test firmware architecture for a novel, flexible, multi-sensor for physiological monitoring. The device is fragile and the hardware components and connections must be verified for functionality before end application firmware evaluation. Additionally, the existing sensor firmware is updated to include a manufacturing test mode for additional system testing.

Due to the need for reducing system size and weight while increasing performance, many military and commercial systems today require high-temperature electronics to run actuators, high-speed motors or generators. Of the many passive devices required to satisfy the needs for a complete high temperature system, none has been more problematic than the capacitor, particularly for larger devices requiring values of several micro- or milli-farads. Here we introduce a polymer metal composite we have recently developed that meets typical aerospace design constraints of high reliability, robustness, light-weight, as well as high temperature (up to 300°C) operation. Our recent discovery of the capacitive behaviour in perfluorinated sulfonic acid polymers sandwiched between metal electrodes has lead to the exciting development of high temperature capable high density passive storage components. These composites exhibit capacitance per unit planar area of ~1.0 mF cm-2or 40 mF/g for a ~100 ¿m-thick polymer substrate, with only a small predictable decrease in capacitance immediately after heating to 100°C followed by constant capacitance up to 300°C. Here we report the design and testing of single step microfabrication of metal electrodes to these polymer composites sandwiched between two thin metal films along with their performance at high temperatures.

Over the last five years extensive test infrastructure has been deployed at Canadian Universities, funded by the Canada Foundation for Innovation (CFI) and managed jointly by CMC Microsystems, located at Kingston, Ontario and Principal Investigators at each of four sites. These test facilities are a part of the National Design Network (NDN) in Canada which has been developed over the last 25 years to serve researchers in the design, fabrication and test of microsystems prototypes. This presentation will outline the capabilities of the laboratories and the accessibility of the equipment through local and remote access. The four specialized laboratories enable the testing of Radio Frequency, Photonics, Mixed-Signal and High Speed Digital systems. About 200 researchers at 23 Canadian Universities participate in this `Testing Collaboratory' and they are connected using a wide area, fiber optic network provide by CANARIE. Hands-on assistance, training and specialist consultation is required for the operation of such sophisticated equipment and this is provided by CMC personnel on-site at each location. Activities include assistance in equipment configuration, sample or DUT management, provision of documentation, configuring of the communications links, development of tools for automation of test and data collection, and protection of Intellectual Property. Finally, a selection of the research that has been enabled by the wide availability of this infrastructure will be presented, including work on optical telecommunications systems, security threats to cryptographic systems, new signal processing techniques and RF MEMS devices.

Methods are suggested and tested to measure and optimize the wireless energy transfer efficiency for mid-range (10-100 cm) inductive coils with relatively low profile using magnetic resonance. These coils can be used to provide energy for wireless sensors and battery-operated devices. It is shown that for every system, a resonance frequency can be identified where the wireless energy transfer efficiency is optimal. Several prototypes are developed and tested as a proof of validity of the proposed technique. It is also shown that by tuning to the optimum resonant frequency and designing proper matching circuitry, an efficiency of about 25% for moderate profiles can be achieved.

We discuss the issue of reliable transmission of bounded streams of data samples over simple wireless channels offered by low-end RF modules. Traditional solutions, i.e., window-based ARQ schemes, applied to such channels tend to waste bandwidth, because of the need to maintain duplex communication. Our case study shows how one can overcome the inherent limitations of low-bandwidth unstructured wireless channels and claim most of their capacity for transmitting useful data.

Many protocols for ad-hoc wireless networks perform poorly in situations when node cooperation cannot be enforced. This may happen because of the lack of global authority over the nodes, or because of the environmental hostility. The net outcome of such scenarios is what we call a selfish behavior of nodes, which may spontaneously refuse to forward some packets. While unicast communication has been studied in this context, little has been done to improve the reliability of broadcasting in the face of limited trustworthiness of nodes. In this paper, we propose two enhancements of the popular broadcasting algorithms based on dominant pruning, which significantly improve the reachability of nodes in an unreliable ad-hoc wireless network. The improvement can be viewed as an enhancement of the network's fault tolerance, as it applies to most scenarios in which a node may fail to carry out its forwarding duties.

BACKGROUND: We previously demonstrated that gene expression profiles during neuronal differentiation in vitro and hippocampal development in vivo were very similar, due to a conservation of the important second singular value decomposition (SVD) mode (Mode 2) of expression. The conservation of Mode 2 suggests that it reflects a regulatory mechanism conserved between the two systems. In either dataset, the expression vectors of all the genes form two large clusters that differ in the sign of the contribution of Mode 2, which for the majority of them reflects the difference between down- or up-regulation. RESULTS: In the current work, we used a novel approach of analyzing cis-regulation of gene expression in a subspace of a single SVD mode of temporal expression profiles. In the putative upstream regulatory sequences identified by mouse-human homology for all the genes represented in either dataset, we searched for simple features (motifs and pairs of motifs) associated with either sign of the loading of Mode 2. Using a cross-system training-test set approach, we identified E2F binding sites as predictors of down-regulation of gene expression during hippocampal development. NR2F binding sites, for the transcription factors Nr2f/COUP and Hnf4, and also NR2F_SP1 pairs of binding sites, were predictors of down-regulation of expression both during hippocampal development and neuronal differentiation. Analysis of another dataset, from gene profiling of myoblast differentiation in vitro, shows that the conservation of Mode 2 extends to the differentiation of mesenchymal cells. This permitted the identification of two more pairs of motifs, one of which included the CDE/CHR tandem element, as features associated with down-regulation both in the differentiating myoblasts and in the developing hippocampus. Of the features we identified, the E2F and CDE/CHR motifs may be associated with the cycling progenitor cell status, while NR2F may be related to the entry into differentiation along the neuronal pathway. CONCLUSION: Our results constitute the first prediction of an expression pattern from the genomic sequence for the developing mammalian brain, and demonstrate a potential for the analysis of gene regulation in a subspace of a single SVD mode of expression.

This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing.

This paper presents a highly effective method for parallel hard fault simulation and test specification development. The proposed method formulates the fault simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach extended by parametric fault testing has been implemented as an automated tools set for IC testing.

Process variation has forever been the major fail cause of analog circuits where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach, extended by hard fault testing, has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx.

This work reports on alternative methods of improving photoreceiver sensitivity as well as gain-bandwidth product in a high-capacity optical transmission system. A wide-band and controllable-gain preamplifier utilizing parallel feedback and the capacitive peaking technique which can enhance the bandwidth and can control the gain keeping output DC voltages constant is presented. PSPICE simulations using a 0.6 /spl mu/m GaAs process give 1.097 GHz bandwidth, 87 dBohms transimpedance gain, 4.5 pA/[Hz]/sup 1/2/ average equivalent input noise current spectral density and 55 mW power consumption.

We present an algorithm for automatically generating minimal test sets for parametric faults in linear analog circuits. In a previous work we elaborated a multifrequency test generation method (TPG) for such circuit faults. The method was formulated as a series of optimization problems that were solved by sequential quadratic programming (SQP) available in MATLAB. Such a standard optimization method processes local information and, consequently, cannot guarantee that the found solution is global. This may lead to a poor test selection. Furthermore, the method is semiautomatic and depends on various parameters that must be selected by an experienced user. In this paper, we propose a method based on constraint logic programming (CLP) using relational interval arithmetic (RIA) to solve these optimization problems as a series of constraint satisfaction problems (CSPs). The method is fully automatic and provides tight and guaranteed bounds on the true range of a multivariable nonlinear function. The correctness of the bounds stems from the enumeration of subdivisions of the function and its variable domains while discarding those subdivisions containing no solution. The tightness (i.e., the closeness to the true range) of the bounds can be refined to any desired degree by increasing the fineness of subdivisions imposed on the variable domains and the stringency of the termination criterion at the cost of an increased CPU time. The TPG method was implemented in CLP (BNR) prolog. The effectiveness of our approach is illustrated on a number of nonlinear functions known to be difficult, and two realistic electronic circuits in the context of TPG. Our algorithm accelerated the computation of the various parameters related to the test of a biquadratic filter by a factor ranging from 11 to 29 as compared to the Monte Carlo method.

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

This paper presents a new built-in self test technique for digital to analog converters (DAC). The technique consists of inserting the DAC under test in an oscillating loop forming a sigma-delta modulator. The DAC distortions are then seen at the sigma-delta output as a digital PDM information. A simple up/down counter converts the PDM output into a digital word that is used as test signature. Functional specifications such as offset, differential nonlinearity (DNL), integral nonlinearity (INL) and dynamic distortions of the DAC can be digitally measured using this technique. As a feature of sigma-delta modulation, the analog circuits used to form the modulator loop (integrator and comparator) do not need to be high performance in terms of accuracy and speed. This characteristic allows the technique to have no limitations for resting high frequency and high resolution DACs. This technique can also be applied to test ADC-DAC pair for applications that require both data converters in the same chip.

Testing delay faults is becoming critical in new deep submicron digital circuits. This paper introduces a new technique for delay and stuck-at fault testing in digital integrated circuits. The proposed technique consists of sensitizing a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all or at least critical paths in the circuit. To establish oscillations, we should make sure that there is an odd number of inverters in the loop. This technique can be used along with scan techniques or be implemented as a built-in self-test technique. Benchmark results confirm the efficiency of the proposed technique. The technique has been implemented in practice for an an 8-bit digital adder on a field programmable device.

Working at high frequency adds to VLSI designers and test engineers many constraints. Many effects which are insignificant at low frequency domain have to be taken into account. These effects alternate considerably the precision of the test, introducing the a new challenge to the test community. The impedance mismatch between the circuit under test output impedance and the characteristic impedance of the transmission line as well as the effect of the lumped capacitance at the input of the tester comparator are among the most important effects. These two effects result as ringings, overshoot and timing delay. In this paper we present a method to eliminate the aberrations of the transmission line effects as well as the influence of the lumped capacitance at the input of the DUT thereby improving the precision of the rest.

In this paper, built-in self-test (BIST) approach has been applied to test digital-to-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, integral nonlinearity (INL), and differential nonlinearity (DNL) errors and monotonicity are tested without using mixed-mode or logic test equipment. An off-line calibrating technique has been used to insure the accuracy of BIST circuitry and to reduce area overhead by avoiding the use of high quality analog blocks. The proposed BIST structure presents a compromise between test cost, area overhead, and test time. By a minor modification the test structure would be able to localize the fail situation. The same approach may be used to construct a fast low cost off-chip D/A converter tester. The BIST circuitry has been designed and evaluated using complementary metal-oxide-semiconductor (CMOS) 1.2 /spl mu/m technology.

The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due mainly to the complexity of analog behavior and the lack of a fault mode. We present a new functional fault modeling technique called the perturbation fault model. The perturbation fault model is based on an estimation of the distance between the responses of the faulty and fault-free circuit and their distributions. The model allows fault abstraction of physical defects through structural fault modeling and perturbation estimation. The fault simulation technique uses a linear estimation of the faulty and fault-free output circuits. Techniques for fault observation and propagation are presented in order to build a hierarchical analog fault simulator.

Built-in temperature sensors increase the system reliability by predicting eventual faults caused by excessive chip temperatures. In this paper, simple and efficient built-in temperature sensors for the on-line thermal monitoring of microelectronic structures are introduced. The proposed temperature sensors produce a signal oscillating at a frequency proportional to the temperature of the microelectronic structure and therefore they are compatible to the oscillation-test method. Design and detailed characteristics of the sensors proposed based on CMOS 1.2 /spl mu/m technology parameters are presented. The fabrication results show a small spread in the nominal oscillation frequency of sensors implemented and a good sensitivity of the oscillation frequency with respect to temperature variations. The sensors proposed require very small power dissipation and silicon area.

Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage and test rate of quiescent current (I/sub DDQ/) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I/sub DDQ/ testing. This paper presents a new BICS suitable for on-line power dissipation measurement and I/sub DDQ/ testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 /spl mu/m technology. Practical results demonstrate that a very good measurement accuracy can be achieved.

This paper describes a new built-in self test (BIST) technique suitable for both functional and structural testing of analog and mixed-signal circuits based on the oscillation-test methodology. Analog-to-digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique for both functional and structural testing. Design of different parts of OBIST structure is also presented. The ADC conversion rate, differential nonlinearity (DNL) and integral nonlinearity (INL) at each quantization band edge (QBE) are tested as functional parameters. These parameters are considered to be the most important functional characteristics of an ADC. Practical experimentation using real-world successive approximation and flash ADCs confirms the accuracy of OBIST for functional testing of ADCs. Simulation results using a 3-bit flash ADC designed using a CMOS 1.2 /spl mu/m technology are also presented. For structural testing, oversampled sigma-delta ADCs are investigated. Both hard and soft faults are considered and some simulation results are presented.

Novel Built-In Self-Test (BIST) approaches for integrated optoelectronic systems are presented The methods are compatible with scan chain design and allow testing the internal functionality of the device, the interconnection between modules, the analog characteristics of the transmitters and receivers and the Bit Error Rate (BER) of the channels. The proposed approaches enable system evaluation under realistic operating conditions (including crosstalk degradation) through BER testing. They can speedup both circuit-level and system-level testing by providing means for accessing different parts of the circuit easily and allowing time-consuming performance tests to be run in parallel with boundary-scan tests. Some preliminary experimental results are presented to confirm the proposed approaches for analog and mixed-signal methods.

The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

In our previous work we elaborated a multifrequency test generation method (TPG) for detecting parametric and catastrophic faults in linear analog circuits. The method was formulated as an optimization problem which was solved by Sequential Quadratic Programming (SQP), a non-linear programming method available in MATLAB. Such standard optimization methods are based on and process local information and consequently cannot guarantee a global optimum. In this paper we propose a method based on Constraint Logic Programming (CLP) that solves the optimization problem in TPG as a series of Constraint Satisfaction Problems (CSPs). Our TPG method is fully automatic and provides right and guaranteed bounds on the global optima of a nonlinear function. The TPG method was implemented in CLP(BNR) Prolog. First, we illustrate the effectiveness of our approach on a number of nonlinear functions known to be difficult, and then we apply it to a realistic electronic circuit in the context of TPG. The two methods produce the same results except for one case where SQP falls into a local minimum. This could lead to a wrong test selection. Moreover, while the TPG took over a week of work using SQP, it was solved in a matter of minutes using CLP.

This paper investigates parametric and catastrophic fault coverage of the oscillation-test strategy. A set of definitions to evaluate the efficiency of a test technique and to quantify the parametric fault coverage is therefore introduced. The oscillation-test strategy is a low-cost and practical test method which is very efficient for built-in self-testing of mixed-signal integrated circuits. Active analog filters are used as test vehicle and therefore design for testability techniques to convert them to oscillators have been presented. Discrete practical realizations and extensive simulations based on CMOS 1.2 /spl mu/m technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead.

A new low-cost test method for analog integrated circuits, called the oscillation test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which deviate the oscillation frequency from its tolerance band can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated, and the test time is very small because only a single output frequency is evaluated for each CUT. The oscillation frequency may be considered as a digital signal and therefore can be evaluated using pure digital circuitry. These characteristics imply that the oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this note, the validity of the proposed test method has been verified throughout various examples such as operational amplifiers, amplifiers, filters, and analog-to-digital converters (ADCs). The simulations and practical implementation results affirm that the presented method assures a high fault coverage.

This paper treats the problem of testing integrated operational amplifiers. The efficiency of a new low-cost vector-less test solution, known as oscillation-test, is investigated. During the test mode, the op-amps are converted to a circuit that oscillates. The oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op-amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some design for testability (DFT) rules to rearrange op-amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented method assures a high fault coverage with a low area overhead.

In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related to the propagation of the analog signal to the input of the ADC and the observation of the digital output of the converter at the output of the digital circuit are discussed. The two means for functional testing are discussed: the histogram and the FFT. To observe the outputs of the ADC at the digital circuit, the inverse function of the digital circuit is computed. This can be done by inverting the transfer function of the digital circuit whenever it is available. In the other case, when the digital circuit structure is available, the inverse of the digital circuit is found by boolean function manipulation.

Integrating design and test presents a good challenge in today's analog circuit manufacturing process. Designs should be made according to the sensitivity of the output to all the components. Furthermore, sensitivity can be used to observe component deviation (soft faults) and hard faults from the output. This paper presents an automated sensitivity analysis tool, called LIMSoft, which offers the possibility of sensitivity computation and analysis in order to design fault-resistant circuits and generate test vectors for both soft and hard faults. Some applications for integrating test and design are also presented.

A new low-cost test method for analog integrated circuits, called oscillation-test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which cause a reasonable deviation of the oscillation frequency from its nominal value can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated and the test time is very small because a limited number of oscillation frequencies is evaluated for each CUT. Due to its digital nature, the oscillation frequency can be easily interfaced to boundary scan. This characteristics imply that oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this paper, the validity of the proposed test method has been verified throughout some examples such as operational amplifiers and analog-to-digital converter (ADC).

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminate the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using CMOS 1.5 /spl mu/m technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converter or high resolution pipelined analog-to-digital converter. The presented BIST shows satisfactory results for 9-bit pipelined analog-to-digital converter.

In this paper the problem of testing high speed CMOS circuits is considered. A test methodology based on a Built-in Self-Test scheme adapted to TSPC circuits is proposed. We show through HSpice simulations on netlists extracted from layout that this scheme can operate at more than 580 MHz. Moreover, an efficient solution to the problem of redesigning an easily testable functionally equivalent logic block to eliminate hard to test and untestable faults in TSPC circuits is introduced.

In this paper a new method is proposed for observing analog test points inside integrated circuits that enables the simultaneous observation of a large number of points. The method permits the removal of the analog multiplexer from the signal path and a reduction of the load introduced at the observed test points. A charge coupled device analog shift register is used to sample input voltage and shift out a charge that is proportional to the input voltage.

As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. In this paper, the feasibility of using VHDL language to model communication protocols is examined, and a modeling methodology for such systems using VHDL is presented. We demonstrate our methodology on the transport protocol ISO/CCITT class O. The resulting model is an appropriate model for the high level design. The paper concludes with a discussion of the importance and future trends in modeling communication protocols using HDLs.

This paper proposes a new approach for designing a cost-effective on-chip Built-in Self-Test (BIST) generator through the use of Cellular Automata (CA) structures. The BIST generator thus designed is used to generate pseudorandom as well as deterministic test vectors. It is shown that no complex control logic is required to obtain either sequence. In addition, the resulting Test Vector Generator (TVG) is very efficient in terms of speed performances and is very regular and testable. Simulation of various benchmark circuits has given good results in terms of hardware size and test application time.

Pseudoexhaustive BIST of sequential circuits consists of breaking all cycles in the circuit, partitioning the obtained acyclic circuit by placing some segmentation cells in the circuit, and balancing the partitioned circuit by introducing (or selecting in the scan path) additional flip-flops as delays in order to apply combinational TPG methods, In this paper, we present a new efficient method for pseudoexhaustive BIST. We first determine the flip-flops that cause the unbalanced structure of the acyclic circuit by using the peripheral retiming and, second, we use these flip-flops for the circuit partitioning. Thus, these flip-flops can be used for both partitioning and balancing problem of the circuit at the same time. We propose an algorithm for a partitioning problem which combines our idea with existing approaches.

An inexpensive Design For Testability (DFT) technique, called Partial Reset (PR), was recently proposed to ease automatic test pattern generation of sequential circuits. In the present paper, we propose a new PR-like method. With this method, flip-flops to be reset are selected in order to ease pseudo-random testing of sequential circuits. Moreover, the control of these reset are condensed on a reduced set of input lines. Therefore, only a small number of additional primary inputs are required. This technique has been evaluated on a large subset of the 1989 ISCAS sequential benchmark circuits and promising results were obtained.

In this work, we present a new approach for the pseudo-exhaustive BIST of synchronous sequential circuits. We first give a characterization of the flip-flops that cause the unbalanced structure of the acyclic circuit using peripheral retiming techniques, and, consequently, both logic optimization and balancing problem are considered and solved in the same phase. Second, the balancing solution is considered as a first step of the partitioning problem. For the remaining balanced circuit, the segmentation edges are selected such that there is a retiming minimizing the number of segmentation cells in the retimed circuit. Experimental results show that our approach significantly reduces the hardware overhead relative to the existing approaches.

In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value /spl plusmn//spl epsiv/. A sine wave generator and two different BISTs are proposed: the defection and translation (DandT) T-BIST approach and the frequency-counter BIST approach. Some experimental results are also presented.

In pseudo-exhaustive testing, the partitioning technique consists of placing segmentation cells in an acyclic sequential circuit in order to reduce the size of cones. These segmentations, which are transparent in normal mode and active during test mode, result in an overhead for the circuit. However, cutting edges containing registers eliminates these secondary effects. In this paper, we present a new approach to the partitioning problem of the synchronous sequential circuits based on the retiming technique. This approach consists in choosing a set of segmentation edges such that there exists a retiming minimizing the number of segmentation cells in the retimed circuit. Thus, for a given size limit of cone, we propose an iterative algorithm for pseudo-exhaustive sequential testing which combines our method with existing approaches. In addition, we prove that the proposed retiming can be considered as a peripheral retiming while at the same time integrating the logic optimization part in the partitioning process. Experimental results on the benchmark sequential circuits show that our approach significantly optimizes the retimed circuit and reduces the number of segmentation cells required in the original circuit.

In this paper, a new design-for-testability technique for sequential circuits is presented. This technique may be considered as an alternative to full scan. The fault coverages obtained with this technique are comparable to those produced by full scan techniques. However, the present method improves full scan in several ways. The application test time of a device is reduced to that of applying parallel vectors at the operational speed. This characteristic of applying test vectors at the operational speed has a positive impact on the test quality. Indeed, a stuck-at test, applied at the operational speed of the circuit, identifies more defective chips than the same test applied at a lower speed. Furthermore, the timing and the area overheads, which are often considered to be serious disadvantages of DFT techniques, are in this case acceptable. With this method, all FFs are replaced with XFF gates. The XFF gate is similar to a T flip-flop without feedback. However, in some cases, when observability problems are still important, a probe observation point is inserted at the pseudo-primary inputs (PPIs).

This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been used in which the rule space is not limited to the linear rules commonly used in CA studies recently. Based on some new notations and new formulations of CA properties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set. The resulting TVG is very efficient in terms of hardware size and speed performance, and is very regular and testable. Simulation of various benchmark combinational circuits has given good results when compared to alternative solutions.>

In this paper, the initialization of sequential circuits using pseudorandom input patterns is addressed. An extended Markov chain model that covers the initialization phase is proposed. This model supports the theoretical framework used to demonstrate that sequential circuits can be initialized with pseudorandom vectors. This leads to a uniform BIST approach in which initialization and testing are performed together with a single pseudorandom generator.>

FPAD, a CAD tool for the design of analog circuits, is presented. For a set of input specifications, FPAD deduces the device sizes that optimize the performance objectives while satisfying the constraint specifications. Fuzzy set theory is used to measure the degree of fulfilment of the objectives and constraints, and hence provides a measure of the design quality. Trade-offs are handled by manipulating the shape of the membership functions that reflect the fulfilment or violation of the performance specifications. FPAD allows the optimization of several objectives simultaneously since multiple objective optimization is used. The mathematical formulation of the design problem is fuzzified to support real-world terms like high, good, small, acceptable, etc. The optimization is based on analytic models to avoid a simulator in the inner optimization loop. Using this approach, a two-stage unbuffered CMOS op amp and a simple emitter follower were designed, with promising results.>

Peripheral retiming (if it exists) is a method for resynthesising synchronous sequential circuits in which all registers are moved to the peripheral edges. In this paper, we propose a simple approach which considers the retiming of a whole circuit and which can be applied to any arbitrary sequential circuit (i.e. where the usual peripheral retiming concept does not hold). This approach consists in moving the maximum number of registers to the peripheral edges of the whole circuit. First, we model the circuit by means of a Petri net (PN) and show that retiming corresponds to fire transitions in the PN. The theoretical results can then be easily justified. Second, we prove that peripheral retiming is equivalent to solving a transportation problem in a weighted bipartite graph (inputs/outputs) and propose an algorithm for the global optimization of sequential circuits. Some examples of circuits are optimized to show the effectiveness of our approach.>

In this paper, a new approach to high-level synthesis testability evaluation is introduced. This approach consists of two phases: abstraction and propagation. In the abstraction phase, the function's primitive testability measures are abstracted from their oBDD representation. Then, the testability measure is propagated to evaluate data path testability and used in the synthesis for testability process. The choice of a testable design and the modification of a data flow during or after the scheduling and allocation phases are shown to be efficient.>

In this paper, a pseudo-random vector compaction technique for sequential circuits is presented. This technique is based on sequential testability measures and the iterative model. The optimum number of circuit duplications is deduced from the testability analysis. The pseudo random vector compaction consists of conserving the vectors that detect faults and the n-1 previous vectors, where n is the optimum number of circuit duplications. The results indicate that fault coverage produced by 200000 pseudo-random vectors is exactly reproduced by a small set of vectors which do not exceed 1000 vectors for almost all the benchmark circuits.>

A technique for multifrequency test vector generation using testability analysis and output response detection by adding a translation built-in self test (T-BIST) is presented. We study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. This testability evaluation will be helpful in generating the test vectors and for selecting test nodes for the various types of faults. In the proposed approach test vector generation and test point selection allow a significant reduction in the number of measured output parameters necessary for testing (to one or two parameters) without a loss in fault coverage. The T-BIST approach consists of verifying whether or not the tested parameters for the given test vector are within the acceptance range. This technique is based on the conversion of each detected parameter to a DC voltage. Results are presented for different practical filters for which a complete test solution was achieved.

The concept and experimental results for the novel optoelectronic architecture of the IC tester allowing very high test rates is presented. This architecture is based on our new alternative approach of encoding the data implying double optical pulses. The validity of the concept has been confirmed with the simulation results. This new method along with optical multiplexing and self-clocked optical distribution resulted in outstanding performance and revealed numerous possibilities for the proposed architecture.

Testability analysis in analog circuits is an important task and a desirable approach for producing testable complex systems. In past years, most of the testability evaluation methods presented were based on measures of the degree of solvability of the fault diagnosis equations. In this paper, we study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. The proposed algorithm indicates the set of adequate test frequencies and test nodes to increase fault observability. We analyze the case of single fault and of double and multiple faults. Concepts such as fault masking, fault dominance, fault equivalence and non observable fault in analog circuits are defined and then used to evaluate testability. Finally, some experimental results are provided.>

Synthesizing a digital system from a functional description is a complex process requiring the solution of various different problems. TASS (Tabu Search Synthesis System) is a functional synthesis system made up of interdependent modules based on new and more efficient algorithms. First, a control and data flow graph model for system representation is developed and presented. This model generates a single graph representing both the data and control flows of a VHDL behavioral description. A new representation of conditional branches and a mutual exclusion testing procedure offering optimized resource sharing and critical path reduction possibilities have been developed. This graph model is an environment used for various synthesis needs starting from high-level transformations to FSM synthesis for controller implementation. A new mathematical formulation of the scheduling problem is developed using a new approach based on penalty weights. This approach avoids the inflexibility of the ILP formulations developed in related works where the functional unit performing each type of operation is fixed prior to scheduling. The Tabu Search technique, which has been effective in finding optimal solutions for many types of large and difficult combinatorial optimization problems, has been adapted for this purpose. This technique, which performs an intelligent and fast solution space exploration, combined with an effective mathematical formulation makes the scheduling algorithm presented here very powerful.>

A new approach for dynamic test vector compaction, for combinational logic circuits, called COMPACT, is proposed. A new data structure of test vectors permits easy verification of compactability between test vectors with minimal memory requirements. Experimental results obtained by adding the proposed algorithm to a simple PODEM program and applying it to the ISCAS-85 benchmark circuits are presented. The resulting test vector reduction is up to 40% for small circuits and around 50% for the large circuits (over 1000 gates).>

Analog circuit testing is considered to be a very difficult task, due mainly to the lack of fault models and accessibility to internal nodes. An approach is presented for analog circuit modeling and testing to overcome this problem. This circuit modeling is based on a sensitivity computation and on circuit structure, which are crucial in analog circuit testing. The testability of the circuit is achieved for the simple fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing both catastrophic and soft faults. Some experimental results are presented.>

An approach of a functional-level testability evaluation, based on controllability and observability measures (c.o.m.), is proposed. Using Rutman's system model, ordinary applied at the gate level, c.o.m are extended to the data-path level, to permit incorporation of testability constraints in the high-level synthesis stage. The approach of computing these c.o.m. is based on the reduced ordered binary decision diagram (ROBDD) circuit representation. It is shown how to identify untestable parts of a data path and how to evaluate its test cost. The insertion of a two-variable multiplexor, as a structural modification in the data path, is suggested to improve the c.o.m., and so, the test cost. To evaluate the impact of this transformation on the data-path testability, an objective function is proposed, appropriate for high-level synthesis.>

A framework for prediction and estimation of the test yield and test cost of VLSI systems during the design-for-testability stage is given. As an important extension, the authors present a technique for evaluating the set of possible solutions and selecting the most effective one. This technique is based on the evaluation of test-related performance measures and on decision theory. As a result, a new level of design and test integration is obtained. Experimental results have confirmed the applicability and effectiveness of the method. It is shown that it is possible to derive, in a very straightforward manner, maximum and minimum expected values of the design yields of a strategy (design scheme).>

A tool for interactively finding hard-to-test nodes and assessing the impact of test points on random pattern testability is described. With this tool, a set of test points which bring the fault coverage to almost 100% was found for the hardest ISCAS benchmark. It is shown that observation test points only are not sufficient, and thus controllable test points are required. The added test points yield test sets shorter than those necessary with weighted random test sets. On the basis of these findings, a pragmatic approach to built-in self-test (BIST) is proposed. New CMOS BILBO-like test latches that are self-tested are also proposed. A modified implementation for the force-observe (F-O) test points is proposed, and an evaluation of the relative overhead associated with both the circular scan path and the added test points is presented.>

A method to identify hard-to-detect combinational logic faults where the hard faults' classification is based on circuit budgetary constraints is proposed. Reusable results, avoiding redundant effort, and no required simulation contribute to the implementation's efficiency. A definition of hard faults, excluding redundant faults, is presented and the algorithms used are described.>