The performance of in-order execution Itanium/sup TM/ processors can suffer significantly due to cache misses. Two memory latency tolerance approaches can be applied for the Itanium processors. One uses an out-of-order (OOO) execution core; the other assumes multithreading support and exploits cache prefetching via speculative precomputation (SP). This paper evaluates and contrasts these two approaches. In addition, this paper assesses the effectiveness of combining the two approaches. For a select set of memory-intensive programs, an in-order SMT Itanium processor using speculative precomputation can achieve performance improvement (92%) comparable to that of an out-of-order design (87%). Applying both 000 and SP yields a total performance improvement of 141% over the baseline in-order machine. OOO tends to be effective in prefetching-for L1 misses; whereas SP is primarily good at covering L2 and L3 misses. Our analysis indicates that the two approaches can be redundant or complementary depending on the type of delinquent loads that each targets. Both approaches are effective on delinquent loads in the loop body; however only SP is effective on delinquent loads found in loop control code.

To achieve higher processor performance requires greater synergy between advanced hardware features and innovative compiler techniques. Recent advancement in compilation techniques for predicated execution has provided significant opportunity in exploiting instruction level parallelism. However, little research has been done on how to efficiently execute predicated code in a dynamic microarchitecture. In this paper, we evaluate hardware optimizations for executing predicated code on a dynamically scheduled microarchitecture. We provide two novel ideas to improve the efficiency of executing predicated code. On a generic Intel Itanium processor pipeline model, we demonstrate that, with some microarchitecture enhancements, a dynamic execution processor can achieve about 16% performance improvement over an equivalent static execution processor.

The authors present a quantitative analysis of the simulated evolution (SE) technique based on a variety of parameters. The measurement results and their relevance to practical implementations are discussed. A mathematical formulation of the SE algorithm is introduced. The associated Markov chain model is thoroughly analyzed. It is shown that the algorithm will hit a global minimum with probability one. The theoretical analysis suggests some modifications to a previously published SE-based method that was applied to cell placement problems. In order to compensate for additional computation times required by the new technique, the authors also introduce a novel hierarchical placement method. It has inherent advantages over the flat method in both CPU time requirements and result quality. It is also shown how a windowing method can be used to significantly reduce computation times.>

This paper presents a mathematical formulation of the Simulated Evolution algorithm, a novel optimization technique, followed by a thorough analysis of the associated Markovchain model. We show that the algorithm will reach a global minimum with probability one, and also introduce a novel hierarchical placement technique. Finally, we describe a Standard Cell placement program based on the new approach whose preliminary results are comparable to the best Simulated Annealing algorithms.

ESP (evolution-based standard cell placement) is a program package designed to perform standard cell placement including macro-block placement capabilities. It uses the novel heuristic method of simulating an evolutionary process to minimize the cell interconnection wire length. While achieving comparable results to popular simulated annealing algorithms, ESP usually requires less CPU time. A concurrent version designed to run on a network of loosely coupled processors, such as workstations connected via Ethernet, has also been developed. For medium to large circuits (>250 cells per processor) concurrent ESP achieves linear speedup.>

ESP (Evolution-based Standard cell Placement) is a new program package designed to perform standard cell placement and includes macro-block placement capabilities. It uses the new heuristic method of simulating an evolutionary process in order to minimize the cell interconnection wire length. While achieving results comparable to or better than the popular Simulated Annealing algorithm, ESP performs its task about ten times faster.