This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The pro- posed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-μm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

The significance of redundant technologies for improving dependability and delay fault testability are growing. So, delay fault testing on two-rail logic circuits well known as a class of redundant technologies will become important. Two-rail logic circuits can be efficiently tested by noncodeword vector pairs. However, noncodeword vector pairs may sensitize some faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with noncodeword vector pairs may be overtesting. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the overtesting. The amounts of test data for the proposed test sets are, on average, 28.2 percent less than those for the test sets, which are obtained by the existing construction for unate circuits and lead to the overtesting.

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.

Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. Especially, quantitative metric of integrity has not been proposed yet. This paper proposes quantitative metric for integrity for remote systems based on the Internet. It is also useful for evaluation of the effect of the measure against data destruction elements. This paper applies it to example systems in order to confirm its effectiveness.

In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate SEUs caused by particles striking feedback loops in the FFs. Moreover, the proposed FFs allow enhanced scan delay fault testing. The proposed FFs are master-slave FFs, and the slave latches are constructed by modifying existing SEU tolerant latches, namely, SEH latches. The two proposed FFs tolerate particles with charges of 370 fC and of 369 fC or lower, whereas an existing SEU tolerant enhanced scan FF, called an ESFF-SEC, tolerates those of 431 fC or lower. Furthermore, the areas of the proposed FFs are 23.1% and 20.5% smaller than that of the ESFF-SEC. The CK-Q delay times are 44.4% and 41.1% shorter than that of the ESFF-SEC. Moreover, the average power consumptions of the proposed FFs during system operations are 55.6% and 53.3% lower than that of the ESFF-SEC.

This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18 ¿m process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.

Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems.For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. This paper proposes security evaluation metric which is a part of RASIS for remote systems using the Internet.The proposed metric gives quantitative evaluation in the similar manner of availability evaluation.It is based on the time that the system can tolerate take-over attack, which is one of the biggest threats among the attacks through the Internet.It can give appropriate system parameters to achieve the desired security.This paper applies it to example systems in order to confirm its effectiveness.

Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword vector pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.

This paper proposes a method providing efficient test compression for delay fault testing using enhanced scan design. In the proposed method, the initial and transition vectors of test data are interleaved before test compression using statistical coding. This paper also shows test architecture for delay fault testing using the proposed method. The proposed method is experimentally evaluated from the viewpoint of compression rates. For robust testable path delay fault testing on 11 out of 23 ISCA589 benchmark circuits, the combination of Huffman coding and the proposed method provides higher compression rates than Huffman coding without the proposed method, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC)

A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. Prior to test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a shared test set with minimum size. During test, the on-chip scan chain disable signal (SCDS) generator is employed to retrieve the original test vectors from the shared test set. The approach is non-intrusive and automatic test pattern generator (ATPG) independent. Moreover, the approach can reduce test cost further by combining with general test compression/decompression technique. Experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.

This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-I, a coarse grained dynamically reconfiguration processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead

A novel concurrent core test approach is proposed to reduce the test cost of SOC. Prior to the application of test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a minimum size of merged test set. During test, the proposed scan tree architecture is employed to support the concurrent core test using the merged test set. The approach achieves concurrent core test with one scan input and low hardware overhead. Moreover, the approach does not need any additional test generation, and it can be used in conjunction with general compression/decompression techniques to further reduce test cost. Experimental results for ISCAS 89 benchmarks have proven the efficiency of the proposed approach.

In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.

This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the proposed design is also shown. This paper evaluates the proposed design from the view point of the yield, area and delay time. For example, the yield of a 32 /spl times/ 32 Wallace multiplier increases from 0.90 to 0.99 by applying the proposed design while the area increases by a factor of 1.89.

Parallel computers are now popularly applied to applications where many calculations are required. In a NO Remote memory Access model (NORA) parallel computer, many processors are connected by communication links and calculation results are obtained by communications among processors. The message switching method, which controls message transmission in the parallel computer, is one of the most important parameters to improve the performance of the parallel computer. Since parallel computers include many processors, its failure rate is very high and many fault-tolerant switching methods have been proposed. The existing methods have problems, however, such as low communication throughput, low fault-tolerant capability, and large hardware overhead. We propose fault-tolerant switching by improving wormhole switching. The proposed method inserts dummy flits, having no information, after the header flit, the first flit of the packet. By overwriting the header flit to the dummy flit, backtracking is implemented without hardware overhead. Computer simulation says that in a 16 by 16 2D torus, for example, the throughput of the proposed method is almost equal to that of existing methods which require large hardware overhead if the number of the faulty nodes is less then 40.

In this paper, a novel hybrid built-in self-test (BIST) approach for system-on-a-chip (SOC) test using an embedded FPGA core is presented. The hybrid BIST combining pseudorandom test with deterministic test can achieve not only complete fault coverage but also minimal test cost by selecting the appropriate number of pseudorandom patterns. Most importantly, the FPGA-based hybrid BIST has minimal hardware overhead, since after testing, the FPGA core can be reconfigured as normal mission logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach.

Topics related to the faults in SRAM-based field programmable gate arrays (FPGAs) have been intensively studied in recent research studies. These topics include FPGA fault detection, FPGA fault diagnosis, FPGA defect tolerance, and FPGA fault tolerance. This paper provides a guided tour to the approaches related to these topics. These include techniques, which are applied to the FPGA and others which have been recently introduced and can be applied to today's FPGAs.

In delay fault detection BIST (built-in-self-test), an adjacency test pattern generation scheme can generate robust test patterns effectively. Traditional adjacency test pattern generation schemes use an LFSR (linear feedback shift register) to generate initial vectors but they cannot handle circuits with more than 30 inputs. In this paper, a determined BIST scheme, where several seeds are applied, is proposed. Based on analysis of independent partial circuits in the circuit under test, an algorithm is used to generate the seeds - the small number of necessary initial vectors. Through combining outputs of the shift register, the number of shift register stages is reduced. Experiments show that the method of this paper has maximum fault coverage, and short test length that means short lest time. The hardware overhead is at the same level as traditional methods.

As a network topology for a massively parallel computer system, generalized hierarchical completely-connected networks (HCC), which include conventional hierarchical networks, have been proposed. To apply an HCC to a parallel computer system effectively and to execute data processing on the HCC efficiently, the inherent fault-tolerant properties in the HCC must be revealed. However, the properties have not been clarified enough. In this paper, the properties, such as node-connectivity, node-disjoint paths or container, and wide/fault diameter, are verified for the HCC. The concept of the block-connectivity related to the node-connectivity of HCC is introduced, and the fault-tolerance of HCC is discussed. Furthermore, to clear those properties of HCC the unknown properties of other hierarchical networks are also cleared. As a result, the HCC has a fault-diameter that is about 1.5 times as long as the diameter of HCC.

Recently, parallel computing has been applied to many systems. Functional programming is suitable for parallel programming because of referential transparency and is applied to symbol processing systems and parallel database systems. Programs with some functional programming can be regarded as graphs and are processed in terms of reduction of the corresponding graph. The paper proposes fault tolerance of functional programming based on graph reduction. The proposed method stores the received graph as a message log and an erroneous task is recovered by using the checkpoint and the stored graph. Computer simulations reveal that the time overhead of the proposed method is small. If the checkpoint interval is 30 seconds and the number of tasks is 3, for example, the time overhead is less than 10%.

A routing strategy for suspensive deadlock recovery called an escape-restoration routing is proposed and its performance is evaluated. In the principle of the proposed techniques, a small amount of exclusive buffer (escape-buffer) at each router is prepared for handling one of the deadlocked packets. The transmission of the packet is suspended by temporarily escaping it to the escape-buffer. After the other deadlocked packets were sent, the suspended transmission resumes by restoring the escaped packet. Evaluation results show that the proposed techniques can improve the routing performance more than that of previous recovery-based techniques in handling deadlocks.

Proposes a test strategy for FPGAs to be applied within FPGA-based fault-tolerant systems. We propose to make some configurable logic blocks (CLBs) under test and to implement the rest of the CLBs with the normal user data. In the target fault-tolerant systems, there are two phases (the functional phase and the test phase). In the functional phase, the system achieves its normal functionality, while in the test phase, the FPGA is tested. In this phase, the configuration data of the CLBs under test are shifted on-chip in parallel to other CLBs for achieving the test in these CLBs. All the CLBs are tested in a single test phase. The shifting process control, test application and test observation are achieved by the logic managing the fault tolerance (from outside the chip). The system returns to its normal phase after all the CLBs have been scanned by the test. The application of this approach reduces the fault tolerance cost (hardware, software, time, etc). The user is then able to periodically test the chip using only the data inside the chip and without destroying the original configuration data. No particular hardware is required for saving the test data on-board. Additionally, no particular software treatment is required for the test. The testing time is reduced enormously. Unfortunately, as a consequence of implementing two types of data on-chip, a 15% decrease in the chip functionality and a 2.5% delay overhead are noticed in the case of structures similar to a 20/spl times/20 Xilinx FPGA.

This paper presents a new design for testing SRAM based field programmable gate arrays (FPGAs). The new proposed method is able to test both the configurable logic blocks (CLBs) and the interconnection networks. The proposed design is based on slightly modifying the original SRAM part in the FPGA so that it will allow the configuration data to be looped on a chip and then the test becomes easier. This method requires a very short test time compared to the previous works. Moreover, the off-chip memory used in the storage of the configurations data is considerably reduced. The application of this method to the XC4000 family and ORCA shows that (relative to that required by the previous works) the test time can be reduced by 87.2% and the required off-chip memory can be reduced by 88.6%.

This paper presents a new design for testing and diagnosing the SRAM-based field programmable gate arrays (FPGA). By slightly modifying the original FPGA's SRAM memory, the new architecture permits the configuration data to be looped on a chip. Then the full testing and diagnosing of the FPGA are achieved by loading typically only one testing configuration datum (carefully chosen) instead of loading the total required configurations data (which is a very slow process) in the normal cases. Other configurations data are obtained by shifting the first one inside the chip. Consequently the test becomes faster. This method does not need a large outside memory (off-chip memory) for the test. The evaluation proves that this method becomes very interesting when the complexity of the configurable blocks (CLBs) or the chip size increase.

Recently various mobile stations become widely available due to the advance of communication and computer technologies. Because of the mobility of terminal devices and the bandwidth limitation of wireless networks, it is difficult to apply traditional error recovery schemes for fixed networks to mobile network environments directly. So, several recovery schemes for mobile environments have been proposed. They are improved versions of the backward recoveries, especially the checkpointing and the message logging. However these schemes consider either the total cost or the recovery time. In this paper we propose two new schemes which consider both of the cost and the time.