Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Sunpyo Hong

dblp:88/7113 · DBLP profile ↗
← Back
6ranked-venue papers
2as first author
2since 2021 · last 2024
0009-0003-0743-0521ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 3 · 2 first-authorArtificial intelligence and machine learning · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Energy-efficient computing · 32% GPUs and heterogeneous computing · 19% Performance modeling and evaluation · 17%

Topics — the 12 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing
GPU power consumption
0.112010
An integrated GPU power and performance model · ISCA 2010
GPUs and heterogeneous computing
GPU power modeling
0.112010
An integrated GPU power and performance model · ISCA 2010
Energy-efficient computing
power management
0.112010
An integrated GPU power and performance model · ISCA 2010
Energy-efficient computing
power-performance modeling
0.112010
An integrated GPU power and performance model · ISCA 2010
Performance modeling and evaluation
analytical modeling
0.112009
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness · ISCA 2009
GPUs and heterogeneous computing
GPU architecture
0.112009
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness · ISCA 2009
Performance modeling and evaluation › processor performance modeling › accelerator performance modeling
GPU performance modeling
0.112009
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness · ISCA 2009
Processor architecture and microarchitecture › multiprocessor architecture
heterogeneous multiprocessor
0.112009
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping · MICRO 2009
Memory systems › memory access optimization
memory-level parallelism
0.112009
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness · ISCA 2009
Parallel and multicore computing
parallel programming models
0.112009
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping · MICRO 2009
Processor architecture and microarchitecture
many-core architecture
0.012010
An integrated GPU power and performance model · ISCA 2010
Parallel and multicore computing
thread-level parallelism
0.012009
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness · ISCA 2009

Methods — techniques the papers use, named apart from their topics

adaptive mapping · 0.1
YearPublicationVenuePosition
2024 Hierarchical Action Chunking Transformer: Learning Temporal Multimodality from Demonstrations with Fast Imitation Behavior
abstract
Behavioral cloning from human demonstrations has succeeded in programming a robot to generate fine-grained motion, but it is still challenging to learn multimodal trajectories such as with various speeds. This restricts the use of a robot dataset collected by multiusers because the different proficiency of robot operators makes the dataset have diverse distributions of speed. To tackle this issue, we develop Hierarchical Action Chunking Transformer with Vector-quantization (HACT-Vq) to efficiently learn temporal multimodality in addition to fine-grained motion. The proposed hierarchical model consists of a high-level policy to make planning for a latent subgoal and style, and a low-level policy to predict an action chunk conditioned with the latent subgoal and style. The latent subgoal and style are trained as discrete representations so that high-level policy can efficiently learn multimodal distributions of demonstrations and retrieve the mode of fast behavior. In experiments, we set up bimanual robots in both simulation and real-world environments, and collected demonstrations with various speeds. The proposed model with the quantized subgoal and style showed the highest success rates with fast imitation behavior. Our code is available at https://github.com/SamsungLabs/hierarchical-act.
J. Hyeon Park, Wonhyuk Choi, Sunpyo Hong, Hoseong Seo, Joonmo Ahn, ChangSu Ha, Heungwoo Han, Junghyun Kwon
IROS3
2021 GhostPose*: Multi-view Pose Estimation of Transparent Objects for Robot Hand Grasping
abstract
Pose estimation is a key challenge in robot manipulation and grasping task. Current object pose estimation approaches based on 3D models and depth sensor information have difficulties to handle transparent objects because of the limitation to capture the accurate depth information. To address these issues, we present a 6DoF pose estimation approach, called GhostPose, which utilizes a novel 3D bounding box prediction network and multi-view geometry with cameras on manipulator robot. Our 3D bounding box prediction network is simple and light-weight by adding a small branch to a one-stage object detector. The network detects 2D projections of 3D bounding box vertices. Then, 3D points are reconstructed from the 2D results of the multiple viewpoints with camera motion information, i.e. extrinsic parameters, calculated from the robot joint angles. We also present generalized pose definition to address pose ambiguity of symmetric objects and keep consistency of geometric properties around feature points across both of the symmetric and asymmetric objects. Comparing with the previous pose estimation approaches, GhostPose is more generalized to environments and object types, because it does not require 3D models, object specific key points, predefined stereo settings and depth map. In experiments, it outperforms a state-of-the-art approach and shows generalized properties by applying to a real manipulator robot grasping system.
Jaesik Chang, Seongmin Kang, Heungwoo Han, Sunpyo Hong, Kyunghun Jang, Sungchul Kang
IROS5
2018 Performance Characterisation and Simulation of Intel's Integrated GPU Architecture
abstract
Integrated GPUs (iGPUs) are ubiquitous in today's client devices such as laptops and desktops. Examples include Intel's HD or Iris Graphics and AMD's APUs. An iGPU resides on the same chip as the CPU, which is in contrast to a conventional discrete GPU that would typically be connected over the PCI-E bus. Much like discrete GPUs, iGPUs are also capable of general purpose computation in addition to traditional graphics roles. Further, iGPUs have some interesting differences compared to traditional GPUs such as a cache-coherent memory hierarchy and a shared last level cache with the CPU. Despite their wide spread use, they are not studied very extensively. To the best of our knowledge, this paper introduces the first open source trace generation and microarchitectural simulation framework for Intel's integrated GPUs. We characterise the performance of Intel's Skylake and Kabylake GPUs through detailed microbenchmarks, and use the performance evaluations to guide our models and validate the simulator.
Prasun Gera, Hyojong Kim, Hyesoon Kim, Sunpyo Hong, Vinod George, Chi-Keung Luk
ISPASS4
2010 An integrated GPU power and performance model
abstract
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a challenge for programmers. Furthermore, optimizing for power consumption is even more difficult. Unfortunately, as a result of the high number of processors, the power consumption of many-core processors such as GPUs has increased significantly.
Sunpyo Hong, Hyesoon Kim
ISCA1
2009 An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
abstract
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Programming thousands of massively parallel threads is a big challenge for software engineers, but understanding the performance bottlenecks of those parallel programs on GPU architectures to improve application performance is even more difficult. Current approaches rely on programmers to tune their applications by exploiting the design space exhaustively without fully understanding the performance characteristics of their applications.
Sunpyo Hong, Hyesoon Kim
ISCA1
2009 Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping
abstract
Heterogeneous multiprocessors are increasingly important in the multi-core era due to their potential for high performance and energy efficiency. In order for software to fully realize this potential, the step that maps computations to processing elements must be as automated as possible. However, the state-of-the-art approach is to rely on the programmer to specify this mapping manually and statically. This approach is not only labor intensive but also not adaptable to changes in runtime environments like problem sizes and hardware/software configurations. In this study, we propose adaptive mapping, a fully automatic technique to map computations to processing elements on a CPU+GPU machine. We have implemented it in our experimental heterogeneous programming system called Qilin. Our results show that, by judiciously distributing works over the CPU and GPU, automatic adaptive mapping achieves a 25% reduction in execution time and a 20% reduction in energy consumption than static mappings on average for a set of important computation benchmarks. We also demonstrate that our technique is able to adapt to changes in the input problem size and system configuration.
Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim
MICRO2