Communications systems continuously generate a big number of alarms. Such alarms are usually monitored by network operations centers (NOCs) from where steps to resolve the causes are launched either automatically or through a ticketing system. In order to respond to a practical number of alarms in real-time, automation is a must. This problem is more so in virtualized infrastructure since the number of alarm generating entities in such networks is significantly increased because their monitoring has to be performed for both physical as well as virtual functions. In this paper, we propose MAYOR: a suite of machine learning and analytics algorithms for automated operations and recovery. MAYOR is made up of a model generation entity which uses long term historic data to determine alarm persistence times, clusters, and patterns. To this, we model alarm persistence time as a normal distribution, and use the resulting cumulative distribution function to determine the time with an appropriate confidence. Moreover, we use sequential pattern mining and linear correlation to create alarm clusters. Finally, decision trees are used to create patterns between alarms as association rules. In addition, the system also has an adaptation entity that uses realtime alarms to perform short term adaptations. MAYOR has been implemented and evaluated using real telecommunications network alarm data as well as NOC settings. Evaluations show that the proposed persistence times can reduce 20% of static ones by atleast 80%, and that at least 23% of alarms can be predicted 1 hour before they appear with an accuracy of at least 80%.

Kaleido is a system for flexible concurrent processing of multimedia flows where applications are decomposed into building blocks called "active buffers" whose computation and I/O requirements are characterized so as to allow reservation of CPU and bandwidth resources. The input and output ports of active buffers in a Kaleido application are connected by channels. The active buffers in an application may themselves be mapped either to a single compute node, or to multiple compute nodes connected by a network. The Kaleido runtime system software transparently handles the resulting local and remote channels by providing the abstraction of a distributed "active backplane". This "active backplane" also allows dynamic applications whose functional partitioning among compute nodes can be adapted to network, server, and terminal resources. The paper also describes I/O-centric hardware extensions that we have developed for efficient handling of concurrent multimedia streams in Kaleido.

Several emerging applications need a high performance, main memory database for which typical memory systems may be inadequate. In particular, the processor memory bandwidth proves to be a major performance limiting factor. We present the design of a back end object oriented database board and argue for its use in implementing high performance, real time applications. Our board uses programmable logic enhanced memory (i.e., data memory with select computing abilities) which is a novel way to obviate the low bandwidth problem for data intensive processing. Our efforts differ significantly from database machines by being more general purpose and targeting the bandwidth issue at a different level of the memory hierarchy. We describe the utility of logic enhanced memory in meeting the needs of high performance databases.

In order to execute a database program written in sequential code efficiently on a parallel processor, we develop the use of transaction concurrency control paradigms to resolve data dependencies dynamically.The sequential code is divided into small units for execution, and these units are executed concurrently as separate "transactions."Our approach en.sures that the concurrent execution of the smaller units is logically equivalent to the original sequential program.We present an order-preserving concurrency control strategy to execute concurrently the nested invocations that are generated by the parallelized execution of the database program.We present performance figures from a preliminary implementation to indicate the benefits of our strategy.Finally, we provide a rough analysis to gauge the overheads associated with our approach that would impact performance in a full-fledged implementation.1

We describe a network element based on an active memory named SWIM (Structured Wafer-based Intelligent Memory), designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to interact with a disk or a communication line through a backend port. The processing logic is specially designed to perform operations such as pointer dereferencing, memory indirection, searching and bounds checking efficiently. The network element is built using an interconnected ensemble of such memory logic pairs. A complex processing task can now be distributed between a large number of small memory processors each doing a sub-task, while still retaining a common locus of control in the host CPU for higher level administrative and provisioning functions. We argue that active memory based processing enables more powerful, scalable and robust designs for storage and communications subsystems, that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year.>

The authors define memory participative architecture as one in which the memory is not just a passive repository of data, but actively participates in completing a computation along with the CPU. They describe such a system based on an intelligent memory called SWIM, designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to communicate directly with a disk or communication line. A complex communication task can be distributed between a large number of small memory processors each doing a sub-task, while still retaining a common locus of control for operation, administration and maintenance functions. This enables more powerful, scalable and robust designs for communications subsystems that can support emerging network services, multimedia workstations and wireless PCS systems.>

We describe a multiprocessor system that attempts to enhance the system performance by incorporating into its architecture a number of key operating system concepts. In particular:

Recent advancements in high-speed sold-state switching technology have created considerable interest in automatic switching of computation modules within analog computers under the control of digital computers. In this description of work done in "autopatching" of analog computers, relationships are derived among the parameters of a 3-stage asymmetrical connection network which will minimize the number of switches required and yet leave the network rearrangeable or effectively nonblocking. The problem of routing connections through a 3-stage network in presence of fan-out is also considered. The assignment problem is viewed as a mapping of the input terminal set onto the output terminal set. An algorithm is presented which employs mapping operations to resolve blocking conflicts systematically as they are encountered.