Research for Brain-Computer Interfaces (BCIs) has rapidly developed in recent years. Significant advances in this field include brain-controlled bionic limbs and wheelchairs. With these devices, there is a potential benefit for patients with neurologic and neuromuscular diseases, such as Amyotrophic Lateral Sclerosis (ALS). ALS involves the degeneration of motor neurons rapidly over time, leading to paralysis and loss of speech. BCIs have the potential to allow ALS patients to continue to communicate and move with the help of subvocal speech classification and motor imagery control applications. Despite the promise of these devices to improve the quality of life, we must evaluate the ethical implications that will arise due to the advancement of these devices. More advanced and accurate devices that can restore speech could also easily be used to read or listen in on the thoughts of its users, thereby presenting a unique question of ethics. In this paper, we will discuss the current progress, trends, and future ethical implications of current advancements in BCIs. We will also introduce a conceptual BCI-based device with emotion classification, subvocal speech classification, and motor imagery applications.

The functionality of Fused multiply add (FMA) design can be formally verified by comparing its register transition level (RTL) implementation against its system level specification often modeled by C/C++ language using sequential equivalent checking (SEC). However, C-RTL SEC does not scale for FMA because of the huge discrepancy existed between the two models. This paper analyzes the dissimilarities and proposes two intermediate models, one abstract RTL and one rewritten C model to bridge the gap. The original SEC proof are partitioned into three sub-proofs among intermediate models where a variety of simplification techniques are applied to further reduce the complexity. Experiments from an industry project show that with the two intermediate models, the SEC proof is complete and scalable for FMA design.

In this paper, I describe a methodology and tool flow for using formal verification effectively to reduce the verification burden in large custom ASIC designs.

Provides a simple formal model for Itanium/sup TM/ shared memory consistency covering a core set of instructions, that is reverse-engineered fromand. Our model sheds light on tricky concepts such as causality. It deals with cacheable memory instructions consisting of acquire loads, ordinary loads, release stores and ordinary stores, as well as memory fences. It does not currently handle atomic read-modify-writes, non-cacheable memory or special rules pertaining to data dependencies involving registers. Despite its simplicity, our model captures all published ordering properties of the instructions we consider. While operational models have been proposed for commercial shared memory systems (notably for Sparc V9), a notable feature of our operational model is its use of a few explicit devices such as vector timestamps to clearly describe the tricky notion of causality.

We present a method for computing static slices of concurrent programs in a Unix process environment. As a part of our methodology, we introduce the notion of a Concurrent Program Dependence Graph (CPDG). A CPDG represents various aspects of concurrent programs in a hierarchical fashion. This hierarchical representation lets us compute static slices of programs at different levels of abstraction. Based on our methodology, we have implemented a static slicing tool supporting an option to view slices of programs at different levels of details. Experience with our implementation shows that this approach helps the user get a better understanding of the behavior of concurrent programs. Copyright © 2000 John Wiley & Sons, Ltd.