This paper presents a power, speed and area optimized mini-LED driver integrated in 180 nm CMOS HV process and capable of sinking up to 4mA current. It aims to cover various applications of optoelectronic implants with a single design. The current driver consists of a drain-regulated self-cascode current mirror. An additional carrier sweep-out circuit reduces the mini-LED voltage fall time down to 4.7 ns. The current can be digitally adjusted from 0.5 mA to 4 mA, depending on its use-case. The temperature-compensated current reference provides 0.01 mA with a temperature coefficient (TC) of 210 ppm/°C between -10 °C and 110 °C leading to a TC of 357 ppm/°C for the output current. The successfully performed measurements for circuit under pad constructs revealed a possible size reduction only limited by the dimensions of the on-die processed mini-LEDs of 0.1 mm x 0.2 mm.

Interfacing high-density neural probes, that integrate all the circuitry needed to digitize brain activity in situ, requires a thin and conformal cable. Such wiring must be constrained in size to minimize tissue damage during insertion or due to micro motions when operated in a chronic setting. Reducing the number of traces required to connect these devices leads to thinner and more flexible cables or allows to enhance the data rate by allocating wider traces. A lower number of contacts is also less prone to reliability issues in long-term applications. In this paper, a two-wire bidirectional interface for neural probes is presented that minimizes data overhead for configuration and readout. Moreover, the implemented handshaking protocol is designed to adapt to varying line delays that may occur due to different cable lengths or time-varying environmental effects. The interface has been validated in a prototype ASIC fabricated with a 180 nm CMOS technology and a supply voltage of 1.2 V.

A compressed sensing integrate-and-fire neuron concept for massively parallel recordings is presented which expands the fundamental idea of superimposing timely sparse signals for data compression to any kind of continuous-time signals. Merging compressed sensing and amplitude-to-spike conversion, the proposed approach increases the information density and reduces the channel load. Combining multiple data-compressive neurons as a sensing array, further compression can be achieved when the spikes from different recording sites are superimposed on a single transmission channel. Signal reconstruction quality and transmission channel load are investigated to provide a strategy for selecting the design parameters of the proposed system. A proof-of-concept is presented, where a load per recording channel of 1 % under a relative reconstruction error of 0.32 % (SNR = 25 dB) is achieved.

Integrating sensors within a complete readout system on a single die has become essential to the More-than-Moore philosophy. Mechanical stress, as one of the physical quantities of potential interest, provides various information from simple static to dynamic load. Integration of piezoresistive elements within a complete CMOS system has been achieved in many ways, and ground-laying effects have been studied and described in detail. To bring the mechanical and electrical domains closer together, a new concept is presented that allows an analytical and simulation-based approximation of the sensors’ behavior due to applied mechanical stress as part of established concepts in electronics. It is evaluated based on measured state-of-the-art sensor implementations and used to bring up an alternative architecture with enhanced and on-the-fly adaptive sensitivity. Simulations are used to then further evaluate any model errors due to second-order effects that have been neglected within the design process.

In this paper, we present a 13.56 MHz energy harvester for arterial pressure measurement implants placed at deep distances in human bodies. A 50 μm diameter thin wire is used to fabricate a 150-turn solenoid coil around a PCB stripe with a cross-sectional area of 1.35 χ 1 mm2. The solenoid has a length of 12 mm, low-frequency inductance of 4.75 μH, and series resistance of 8 Ω. With this coil and an 11-stage modified differential-drive rectifier, our harvester achieved 698 nW (-31.56 dBm) sensitivity for unloaded output voltage of 1.88 V and maximum receiver efficiency of >72% at -23.5 dBm available power using 0.0228 mm2silicon area in 180 nm technology. A transmission distance of 21 cm was reached under compliance with the field exposure levels set by the IEEE Std. C95.1-2019.

Closed loop charge balancing is a major concern in secure electrical stimulation since it reduces the risk of electrode dissolution and tissue destruction, which might arise after unbalanced stimulation pulses. This CMOS integrated active charge balancer is based on a consequence-based technique that instantaneously removes excess charges between two consecutive stimulation pulses. For high adaptability to various stimulation scenarios, this balancer provides a widely adaptive power supply compliance that ranges from 6.6 to 40 V, without affecting its instantaneous compensation behavior and efficacy. In order to reach a supply compliance as high as 40 V, a design is elaborated that overcomes the technological high voltage limitations and protects the active components of the used 0.35 μm CMOS process. Thus, an adaptive quad-rail concept has been developed to divide the supply voltage into three subranges. The presented charge balancing circuit consists of a fully differential operational transconductance amplifier and an advanced class-B stage, designed in accordance with the quad-rail concept. For arbitrary applications, further flexibility is provided by incorporating three compensation current limitations of ±500 μA, ±300 μA and ±200 μA. Additionally, two safety limits, ±50 mV and ±100 mV, have been adopted. The power dissipation at 40 V is 19.6 μW only. The layout occupies 0.21 mm2.

The implementation of implantable multi-site neural recording systems is a very challenging task for which area-efficient low-power pre-amplifiers and analog-to-digital converters (ADCs) are needed. For such applications, the design and implementation of an area- and power-optimized continuous-time incremental Delta-Sigma ADC are presented in this paper. The second-order continuous-time modulator features an active RC-integrator based loop-filter of type cascade-of-integrators-with-distributed-feedback with area-optimized passive components. The ADC is implemented in a 0.18 μm CMOS process and achieves a signal-to-noise-and-distortion ratio of 70.8 dB in a bandwidth of 10 kHz. It occupies an area of 0.0045 mm2and consumes a power of 16.6 μW whereby the Schreier figure-of-merit results in 165.4 dB.

Implanted devices in the brain are required for in-vivo experiments with freely moving animals and will become a key element of future neuronal interfaces, e.g. for prosthetic limbs with neural control. To maintain an optimal signal quality and cope with micro motions of the implant or plastic reorganization of the brain, the concept of electronic depth control was developed. It combines the high spatial resolution of neuron-sized electrodes with the processing power of CMOS electronics. Challenges of such CMOS probes with active assistance arise from the fact that each recording site has to be equipped with a gain stage consuming very little area. This work gives an overview of the most recent high-density neuronal probes and presents solutions for area-efficient implementations of analog signal-processing features, like on-line bandwidth variation or autonomous start-up and common-mode referencing.

The design of a CMOS integrator for offset voltage monitoring in implantable neural stimulation systems is presented. It reduces the risk of electrode dissolution and tissue destruction, which might arise from a residual electrode potential after unbalanced high voltage (HV) stimulation pulses. The integrator therefore requires HV robustness and low power consumption at the same time. Monitoring low frequency bio-potentials requests a very large time constant, while keeping the capacitance reasonably small for small chip area. The proposed integrator takes advantage of a transconductance-capacitance (Gm-C) approach. The described architecture is based on HV cross-coupled differential input pairs. Within a wide linear input range of ±3V, a time constant of 7.5 ms is achieved by an overall Gmof 1.6 nS and an integrated capacitance of 12 pF. It features a shift in voltage from a HV input common mode (CM) of 15V to a low voltage (LV) CM of 1.65V. The overall power dissipation of the Gm-C integrator is 16μW and the layout occupies 0.39mm2. The system is designed in a 0.35μm CMOS technology with 30V supply and is verified by BSIM layout-extracted simulations.