Tri-level current-steering digital-to-analog converters (DACs) offer an appealing balance between resolution and static linearity, making them attractive to be employed as feedback DAC in high-resolution continuous-time Delta-Sigma-Modulator (CTDSM). However, they are susceptible to non-linearity caused by dynamic, signal-dependent switching errors degrading the overall performance. While such errors have been thoroughly analyzed in literature for single-bit current-steering DACs, they have not been thoroughly investigated for tri-level current-steering DACs. As a result, this paper investigates the sources of these errors and demonstrates their severity by analysis and simulations employing a tri-level DAC in an exemplary CTDSM. In addition, techniques for mitigating dynamic errors, including device sizing and switching schemes, are discussed to help mitigate the non-linearity.

The design of ultra-low power, highly linear and low noise Delta-Sigma modulators (DSMs) is an active topic in research and industrial application to realize high-resolution analog-to-digital converters (ADCs) for applications such as audio, sensor or IoT digitization. In such DSMs, the first integrator stage usually consumes most of the power, which is why innovative amplifier architectures have been proposed. This paper presents a case study of different state of the art power-efficient operational amplifier (OpAmp) topologies in a 180 nm CMOS technology using a standard 1.8V supply. A detailed comparison is made in terms of power, noise, area, linearity, and design effort, which can serve as a guide for designers when choosing the most suitable amplifier architecture for such application.

The theory of incremental Delta-Sigma (I-DS) converters relies on memoryless operation between consecutive Nyquist samples. This is achieved by resetting the analog loop-filter and digital reconstruction filter every Nyquist period. It is shown that the use of reconstruction filters with negligible first-sample weights opens the possibility of removing the periodic reset from the analog loop filter of incremental Delta-Sigma modulator (I-DSM) while maintaining memoryless operation. The periodic reset can further be removed from reconstruction filters whose impulse response is inherently finite. Combining the two features enables free-running Delta-Sigma (DS) converters to be used in time-domain multiplexing applications and without inter-channel interference.

Continuous-time (CT) Delta-Sigma-Modulators (DSMs) are widely utilized in systems requiring wide bandwidth and high resolution. While opamp-based RC integrators are favoured for their excellent linearity, they introduce low-input impedance and complicate the ADC driver. On the other side, Gm-C integrators provide high input impedance, making them more power-efficient, but they suffer from non-linearity, thereby limiting the input range. This paper explores the limitations of a specific non-linearity cancellation technique applied in DSM system-level. The principles of this technique are reviewed, and the challenges of using it at low oversampling ratio (OSR) are investigated. A theoretical analysis is presented, matching with simulation results.

Multibit (MB) quantization allows high resolution Delta-Sigma modulators (DSMs) with low oversampling ratio (OSR). Furthermore, it allows higher maximum stable amplitude (MSA), achieves reduced jitter sensitivity, and relaxes the dynamic requirements on the DSM loop-filter (LF). However, MB quantization adds a dominant source of non-linearity due to element mismatch in the MB digital-to-analog converter (DAC) which often dominates the performance. State of the art (SoA) presents many calibration techniques, though digital power and area consumption can be high and calibration time be significant. In this paper we target a calibration-free DAC based on dual quantization and propose to employ a Multistage noise SHaping (MASH) Digital-DSM (DDSM) to avoid architectural compromises between the main DSM LF and the DDSM DAC. The implementation trade-offs are illustrated, and stability constraints in both the main LF and the DDSM are addressed. An exemplary implementation is derived and simulated, and the results shall lay the foundation for future circuit implementations of MASH DDSM to realize MB DSM with intrinsically high linearity.

Active RC-Integrators are one of the main building blocks of continuous-time Delta-Sigma-Modulators (CTDSMs). The DC gain and gain-bandwidth product (GBW) of their Operational Ampifiers (OAs) play an important role in the modulator stability and performance in terms of signal-to-quantization-noise ratio (SQNR) as well as spurious-free dynamic range (SFDR). Negative-R assisted integrators have been introduced to reduce the CTDSMs sensitivity to OA non-idealities, where the negative-R has shown linearity improvements in low-power CTDSMs for relatively narrow bandwidth applications. However, the negative-R concept has not been widely applied for wideband applications. Wide-band CTDSMs in particular are more sensitive to the non-idealities of the OA GBW and especially in the associated phase-shift compared to their narrow-band counterparts. This paper provides insight into the effect of negative-R assistance on the GBW of the OA, where it is shown, that the phase-shift of the integrator due to finite GBW is not reduced by the negative-R assistance, and still remains an issue to be considered in the design of a wide-band CTDSMs.

Element mismatch error shaping had been thoroughly studied in free-running Delta-Sigma (DS) ADCs, which enabled using multi-bit quantizer in the loopfilter while shaping the non-linearity errors of the feedback DAC unit element mismatch. A popular shaping technique in free-running DS ADCs is the simple rotational data-weighted averaging (DWA), which was shown to be ineffective in state of the art (SoA) higher order incremental Delta-Sigma (I-DS) ADCs. Hence, prior SoA proposed smart shaping techniques tailored for I-DS ADCs, though adding significant area and power complexity compared to DWA. In this work it is shown that by applying periodic reset to the DWA’s rotation index renders it very feasible and effective for DAC mismatch shaping even in higher order I-DS ADCs without the need of changed algorithms.

This work presents a 600MS/s 10-bit single-channel asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) using a highly linear unit via-based delta-length capacitive digital-to-analog converter (C-DAC). The plain and regular segmented C-DAC structure is presented in detail, which provides close to 13-bit static matching with an area of only 1160 μm2. A Flash ADC is employed to pre-load some MSBs for improved conversion speed while also efficiently utilizing DAC segmentation, which is practically necessary in delta-length-based C-DACs. This ADC architecture can easily be extended to a time-interleaved SAR to fully take advantage of the fast Flash conversion. The ADC was fabricated in a 22nm FDSOI technology and achieves a SNDR of 51.37dB at 600MS/s with near Nyquist input while consuming 3.04mW from a 0.85V supply, which leads to a Walden FoM of 16.74fJ/conversion-step.

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

This paper presents a modified Look-Up-Table (LUT) based DAC foreground calibration for multi-bit continuous-time Delta-Sigma Modulators. The feedback DAC in DSMs is usually a performance bottleneck, as all of its errors directly add at the input node. Fore - or background error correction based on LUT can efficiently eliminate the DAC errors, but can also impose significant circuit overhead in the digital and analog domain. The presented method reduces the correction complexity while maintaining the same performance as current state-of-the-art solutions towards static and dynamic errors.

Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the quantizer come with increased swings and reduced maximum stable amplitude (MSA). In this paper, two bitwise ELD compensation approaches applicable to cascade-of-integrators with distributed feedback (CIFB) loop filters are proposed, which alleviate this problem for SAR and other multi-step quantizers by sequentially feeding bits into the feedback loop when they are available (MSB first, LSB last). Loop-filter equivalence for such bitwise ELD compensation is analytically derived. System-level simulations using Matlab & Simulink for exemplary 4-bit 2nd, 3rd and 4th-order modulators show 40% reduction of the last integrator output swing compared to the conventional direct path compensation. This potentially allows to avoid the swing, quantizer scaling and noise trade-offs due to ELD in state of the art designs.

The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.

The performance of Continuous Time Delta-Sigma Modulators (CT-AEMs) is limited by clock jitter in the outermost feedback DAC. As one solution, FIR-DACs have been introduced to improve the modulators jitter robustness. In literature, those FIR-DACs have been described with equal coefficients for all taps. This paper investigates the effect of using non-equal symmetric taps on the modulators performance. A comparison between the two FIR filters (equal and non-equal symmetric taps) regarding jitter immunity, sensitivity to coefficient mismatch, complexity of the filters and the required compensation filter are presented. Furthermore, the effect of the FIR filters on the modulators dynamic requirements and its STF are discussed. The paper shows that symmetric non-equal coefficients outperform the equal coefficients configuration in all aspects without sacrificing hardware complexity, resulting in an extension of the modulator's jitter immunity limit and reduction of power consumption.

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

Intersymbol interference (ISI) plays an important role in the performance of continuous time delta-sigma modulators(CT-ΔΣM). Different techniques, such as return-to-zero DAC, ISI-shaping or calibration, were proposed in literature to tackle ISI in CT-ΔΣM. This paper investigates the effect of ISI in the outermost feedback digital-to-analog converter (DAC) for three different DAC structures; a single-bit DAC (SB), a multi-bit DAC (MB) and a FIR DAC. For each case, Monte-Carlo simulations were performed plotting the SFDR and SNDR for different rise/fall time mismatch percentages. The paper shows that DAC element mismatch due to rise and fall time variations in MB-DACs is more severe than ISI. However, for FIR-DAC the contrary is observed, the degradation in the performance due to ISI in FIR-DAC can be as severe as in SB-DACs when all FIR-taps are matched with regards to rise/fall time.

Recent state-of-the-art designs have shown that high jitter robustness and low integrator dynamics, thus better linearity can be achieved in a single-bit continuous-time (CT) delta-sigma (ΔΣ) modulator by adapting a finite impulse response (FIR) filter in the feedback digital-to-analog converter (DAC). However, when applying this to CT incremental ΔΣ modulators, after each periodic reset of the loop-filter, the output of each FIR tap is unrelated to the input signal and a certain amount of time is needed to settle back to a normal operation. This results in a severe swing overshoots at the output of the integrators in the initial phase of every incremental ΔΣ conversion cycle, which limits the dynamic range (DR) of the modulator and thus counteracts the benefits of the FIR DAC. This paper describes the challenges that come with acquiring an FIR DAC in an incremental ΔΣ modulator. Additionally, two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator. This allows higher number of FIR taps to be used in an incremental ΔΣ modulator, which is very beneficial to promote high speed/resolution designs.

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.

This paper presents the design of a 4 bit flash quantizer with an alternative low kickback, wide DC range input clocked core comparator. The quantizer is demonstrated within a third order continuous time (CT) ΔΣ modulator operating at an fSof 1GHz with an OSR of only 10. In using the proposed clocked core and output latch, a reduction in current consumption within all preamplifiers and resistor ladder can be established. The schematic based flash quantizer is designed in a 1.2V supply 90nm TMSC process, consumes an overall 1.47 mW, and has a decision time of 132 ps. As demonstrating within the exemplary ΔΣ modulator, a coefficient dependent SNDR of 69.8 dB within a 50MHz bandwidth is achieved. When comparing to other state of the art ΔΣ modulator quantizers it achieves one of the lowest power consumptions.

This paper presents the design of an fully differential current steering DAC for a continuous time (CT) ΔΣ modulators with an all native switched DAC cell. In using the proposed cell a lower load capacitance on the virtual ground node of the integrator, reduced charge injection and clock feed-through is obtained when compared to the commonly used NMOS/PMOS DAC cell, thus resulting in an improved performance and lower ISI sensitivity. The native switched DAC is functionally demonstrated within a third order CT ΔΣ modulator operating at an fSof 1GHz with an OSR of 20. The schematic based DAC is designed in a 1.2V 90nm TMSC process including V-I biasing to track the modulator input resistance. Within the explemary ΔΣ modulator an SNDR of 79.12dB and SFDR of 93.44dB within a 25MHz bandwidth is achieved while only being limited by the thermal input noise of the modulator. When comparing to the commonly used NMOS/PMOS switched cell, an improvement of 3dB and 7.3dB in SNDR and SFDR is achieved with the same area and current.

This paper describes a method to improve the linearity, area or SNR of feedback (FB) compensated Sigma-Delta (ΣΔ) modulators. These performance limiting factors are often related to the outer loop feedback DAC or to the 1stintegrator of the ΣΔ-modulator in a FB-compensated modulator. This work focuses on improvements of the 1stintegrator. The origin of these problems is the output swing of the 1stintegrator, which includes and is dominated by the input signal. This problem is usually solved by increasing the capacitor size of this integrator, which results in an increased area and power. Another common solution is to use a feed-forward (FF) compensated ΣΔ-modulator, where basically only quantization noise is processed by the 1stintegrator. However the drawback of this approach is a usually wide bandwidth and peaking of the modulator's signal transfer function (STF). The proposed solution greatly reduces signal swing at the 1stintegrator, by not affecting the STF. Thus, it takes the advantages of the FF-topology, by keeping the advantages of the FB-topology.

This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No digital correction is needed because linearity of the 2-step-flash ADC is provided by a capacitor-array matching and CDS prevents missing codes due to offset in the MDAC.

In this paper we present a correlation based error estimation technique using a residual test signal for the linearization of multibit feedback DACs of lowpass and bandpass Delta-Sigma analog-to-digital converters. Using residual test signal insertion allows operating in background with only limited loss in peak performance during test. Opposed to dynamic element matching techniques, which are limited by the intrinsic nonlinearities in the feedback DAC, the presented method recovers the performance of highly nonlinear systems back to their ideal resolution.